Question Zen 6 Speculation Thread

[Timmah!]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

 

[coercitiv]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

 

[511]

They MUST call it 9950X3D SUPER

9950X ULTRA PRO AI MAX

 

[DrMrLordX]

9950X3D No Scheduler Problems Edition(tm)

 

[511]

9950X3DX2

 

[Timorous]

9950XX3D.

9950X3DD

9950X3D Dual.

9950X3DXT

 

[HurleyBird]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

Potentially good news for Zen6X3D though.

The worst thing AMD could do is launch this 9955X3D2 and then still only top out Zen6 with a dual-CCD, V-cache on only one of the CCDs part since that would mean a sizeable portion of the people who would otherwise have bought the 10950X3D will wait for the 10955X3D2, given that it's the likely capstone of the AM5 socket.

 

[igor_kavinski]

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

On the contrary, I'm furious. If they had even announced it beforehand, I wouldn't have plumped $800+ on the 9950X3D

I think I'm gonna retire from this stupid CPU buying game for a few years now.

 

[eek2121]

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

He isn’t the only one. Going to be an instabuy for me hopefully.

 

[Timmah!]

On the contrary, I'm furious. If they had even announced it beforehand, I wouldn't have plumped $800+ on the 9950X3D

I think I'm gonna retire from this stupid CPU buying game for a few years now.

I thought you acquired Epyc or something, from some of the recent postings, but did not pay enough attention it seems

 

[Jan Olšan]

9950X3D No Scheduler Problems Edition(tm)

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

 

[igor_kavinski]

I thought you acquired Epyc or something

Nah. Genoa and Turin are way out of my range. I only have Epyc Rome.

Oh well. I guess I'll just have to beg as usual, for the three or four weird benchmarks I'm usually interested in and then practice the Zen of patience until Zen6X3D2 is available or someone sells their used Zen5X3D2 for a good price here. Gonna be a long 2 to 3 year wait. Sigh.

 

[DrMrLordX]

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

Eh maybe that would be better. It really depends on where the 9950X3D is losing performance: scheduler misfires or running out of L3 on CCD0.

 

[Timorous]

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

I had the thought it could be a double stack of cache on 1 CCD.

Maybe the 2 Hi Zen 6 is actually being considered so AMD are testing the waters with a Zen 5 variant that has a 2 Hi stack to evaluate yields, bottlenecks and other issues that may crop up so they have time to fix them. It used to be fairly common to do a pipe cleaner type product on a new node with a known design to work out any snags before deploying a new design on the node.

 

[yottabit]

I’d be tempted to spring for a X3DD (X3D2?) if they actually follow through. I feel like a lot of people forget that many of the buyers of the X950 chips do have productivity workloads in mind and I expect it to make an impact there.

The 16 core chips are mostly for people like me that want a Threadripper but don’t have Threadripper money 😆

Plus the “cool” factor, feels like a nice CPU to have or keep in the collection

 

[aigomorla]

They give the 9900 series a dual X3D and yet they don't even bother on threadripper.

Amd really doesn't want us gamers to have PCI-E lanes.

I would swap platforms so fast if the new dual X3D 9900's had 64PCI-E lanes.

I really don't need the quad chanel DDR5, nor do i need the more cores then i can fit on my windows task manager screen.
I just need those PCI-E lanes and a X3D instruction set on my cache, and i would be that happy little fat kid that had that unlimited supply of cotton candy.

 

[soresu]

I would swap platforms so fast if the new dual X3D 9900's had 64PCI-E lanes.

Is there no kit that can turn 1x PCIe5 lane into 2x PCIe4 lanes?

 

[adroc_thurston]

Is there no kit that can turn 1x PCIe5 lane into 2x PCIe4 lanes?

that's called a PCIe switch and they tend to uhhhhhhh be expensive.

 

[RnR_au]

Is there no kit that can turn 1x PCIe5 lane into 2x PCIe4 lanes?

I think https://c-payne.com/ does it, or used to do them.

I have no relations with them.

 

[LightningZ71]

The chip is called a PLX switch. There's one embedded inside of each motherboard chipset on b650/x670 etc boards already. It's how you get from 4 lanes coming from the cpu to the many lanes and devices hung off of them.

There are dedicated PCIe cards that have them, from 4 lanes to dual m.2 4 lane cards up to massively expensive specialty cards.

There is no major reason that someone couldn't build a motherboard that has a 1:4 ratio PLX chip that expands the x16 peg lanes to 64 lanes across 4-6 slots aside from cost.

 

[Thunder 57]

They give the 9900 series a dual X3D and yet they don't even bother on threadripper.

Amd really doesn't want us gamers to have PCI-E lanes.

I would swap platforms so fast if the new dual X3D 9900's had 64PCI-E lanes.

I really don't need the quad chanel DDR5, nor do i need the more cores then i can fit on my windows task manager screen.
I just need those PCI-E lanes and a X3D instruction set on my cache, and i would be that happy little fat kid that had that unlimited supply of cotton candy.

I'd like more lanes but 64 seems excessive. I say that as a person who is pretty much maxed out on lanes. I had to add a PCIe SATA card to bump them back to six because I have a M.2 SSD.

 

[Doug S]

I'd like more lanes but 64 seems excessive. I say that as a person who is pretty much maxed out on lanes. I had to add a PCIe SATA card to bump them back to six because I have a M.2 SSD.

Well think about the reason why PCIe 6.0 was finalized three years ago and there's still pretty much nothing out there for it - it is a lot more expensive to deal with because of the switch from NRZ to PAM-4.

So if you want to keep costs down for boards when you get CPUs able to do PCIe 6.0 you split each 6.0 lane into two 5.0 lanes, and sell boards where everything is PCIe 5.0 without lane sharing. People who just gotta have 6.0 can pay $750 for their boards (not because it costs that much more to make but because it'll be a niche product for the really high end) and everyone else will get more more 5.0 lanes than they need (especially once you add the ones the chipset provides) and 5.0 is more than good enough for almost everyone. The people who pay $4000 for the first PCIe 6.0 dGPU or want 6.0 SSDs that run so hot they need their own cooler will have to fork over for a board that doesn't split the 6.0 lanes into 5.0.

 

[biostud]

On the contrary, I'm furious. If they had even announced it beforehand, I wouldn't have plumped $800+ on the 9950X3D

I think I'm gonna retire from this stupid CPU buying game for a few years now.

Hence the reason I'm not going to upgrade until next generation socket is released. Then I should be able to buy a CPU for a good price for current setup. (also I really don't have any reason to upgrade)

 

[Joe NYC]

Hence the reason I'm not going to upgrade until next generation socket is released. Then I should be able to buy a CPU for a good price for current setup. (also I really don't have any reason to upgrade)

I don't think I will be able to resist the 12 core Zen 6 at 7 GHz with 2 layers of V-Cache. 😉

 

[adroc_thurston]

I don't think I will be able to resist the 12 core Zen 6 at 7 GHz with 2 layers of V-Cache. 😉

You're getting 1-hi with 6.5.
Enjoy