Question Zen 6 Speculation Thread

[Timmah!]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

 

[coercitiv]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

 

[511]

They MUST call it 9950X3D SUPER

9950X ULTRA PRO AI MAX

 

[DrMrLordX]

9950X3D No Scheduler Problems Edition(tm)

 

[511]

9950X3DX2

 

[Timorous]

9950XX3D.

9950X3DD

9950X3D Dual.

9950X3DXT

 

[HurleyBird]

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way

i wonder if this is true. But if it is, its a year too late, at least as far as i am concerned. Firmly waiting for Z6 and potential 24C at this point.

Potentially good news for Zen6X3D though.

The worst thing AMD could do is launch this 9955X3D2 and then still only top out Zen6 with a dual-CCD, V-cache on only one of the CCDs part since that would mean a sizeable portion of the people who would otherwise have bought the 10950X3D will wait for the 10955X3D2, given that it's the likely capstone of the AM5 socket.

 

[igor_kavinski]

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

On the contrary, I'm furious. If they had even announced it beforehand, I wouldn't have plumped $800+ on the 9950X3D

I think I'm gonna retire from this stupid CPU buying game for a few years now.

 

[eek2121]

@igor_kavinski is on the floor, drowning in his own tears of joy.

They MUST call it 9950X3D SUPER

He isn’t the only one. Going to be an instabuy for me hopefully.

 

[Timmah!]

On the contrary, I'm furious. If they had even announced it beforehand, I wouldn't have plumped $800+ on the 9950X3D

I think I'm gonna retire from this stupid CPU buying game for a few years now.

I thought you acquired Epyc or something, from some of the recent postings, but did not pay enough attention it seems

 

[Jan Olšan]

9950X3D No Scheduler Problems Edition(tm)

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

 

[igor_kavinski]

I thought you acquired Epyc or something

Nah. Genoa and Turin are way out of my range. I only have Epyc Rome.

Oh well. I guess I'll just have to beg as usual, for the three or four weird benchmarks I'm usually interested in and then practice the Zen of patience until Zen6X3D2 is available or someone sells their used Zen5X3D2 for a good price here. Gonna be a long 2 to 3 year wait. Sigh.

 

[DrMrLordX]

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

Eh maybe that would be better. It really depends on where the 9950X3D is losing performance: scheduler misfires or running out of L3 on CCD0.

 

[Timorous]

But what if it is 160MB dual-stack cache dies under one CCD and still plain 32MB CCD for the other 8 cores? I doubt I was the only one who got the idea.

You may not like it but this may be what peak performance looks like. You would not see a performance degradation in the vast majority of common application software due to the lowered clocks (that you would get with 96MB+96MB CPU) AND the gaming performance might be better than on a symmetrical 96MB+96MB config. I think there is a pretty high chance of that being true, but I have no idea what the chance of the product being like this is - likely small.

Would be *fun*. Ugly but effective, like the 7950X3D/9950X3D scheme after all.

I had the thought it could be a double stack of cache on 1 CCD.

Maybe the 2 Hi Zen 6 is actually being considered so AMD are testing the waters with a Zen 5 variant that has a 2 Hi stack to evaluate yields, bottlenecks and other issues that may crop up so they have time to fix them. It used to be fairly common to do a pipe cleaner type product on a new node with a known design to work out any snags before deploying a new design on the node.