• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

Question Zen 6 Speculation Thread

Page 214 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
I wonder if they will increase the downstream link bandwidth to the chipset? 4 x PCIe 4.0 is a bit slow at the moment. 4 x PCIe 6.0 would keep pin count low while quadrupling bandwidth and would be manageable as it's all inside the board. If they could then give us 4-8 more exposed lanes downstream, doesn't even have to be PCIe 5.0 either.
 
Well, at one point, the rumor mill had great divergence between consumer CCDs and server CCDs, to the point that all mobile and mainstream desktop parts were going to have the cut down mobile Zen5 core AVX-512 implementation and only Threadripper and server would have the full thing.
 
That was the rumour that desktop will share mobile rather than server
That would be mobile part re-purposed to be used in desktops, the only reason server parts won't be used in desktops is if say Intel fails and AMD will need more server parts, though in this case I reckon they will have other bottlenecks than chiplets, but who knows, big money can solve lots of problems quick.
 
the only reason server parts won't be used in desktops is if [...]
Actually, already since Zen 5, desktop CCDs are no longer used in servers (IOW they come from separate manufacturing batches; they are no longer merely different bins), apparently because the frequency target of desktop caused AMD to tune the desktop CCD transistors way outside server comfort zone.

Any updates about the AVX512? Will the implementation be the same in Zen6 desktop as in Zen5 desktop?
My guess: Yes. Reasons: N2P; and Strix Halo precedence.
Edit: And engineering can explain it to bean counters by mentioning "AI".
 
Last edited:
It seems to me that this is just parametric binning,
For what it's worth, the stepping denominations differ too, apparently. I admit that I have only seen 3rd parties saying that these are made differently, and that this is counter to AMD's modus operandi until Zen 4 inclusive. {edit: see next post}

[Also keep in mind that even Strix Halo, regardless of its low volume, has got its very own special CCD which is not interchangeable with Granite Ridge or Turin. This is in contrast to Zen 4 MI300A and MI300C which (according to AMD) have the same CCD as Genoa and Raphael despite their different GMI physical implementation.]
 
Last edited:
Back
Top