LightningZ71
Platinum Member
- Mar 10, 2017
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I wonder if they will increase the downstream link bandwidth to the chipset? 4 x PCIe 4.0 is a bit slow at the moment. 4 x PCIe 6.0 would keep pin count low while quadrupling bandwidth and would be manageable as it's all inside the board. If they could then give us 4-8 more exposed lanes downstream, doesn't even have to be PCIe 5.0 either.