Question Zen 6 Speculation Thread

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Josh128

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Oct 14, 2022
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sorry to put your hopes down but Intel has a bLLC variant without having to limit themselves to X3D frequency limitations they would have other issue though
X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.
 

511

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Jul 12, 2024
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X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.
ofc it is it's just the limit is higher now also regarding the expensive part they can charge a premium if it has best gaming perf as for higher latency than x3D that's not necessary if anything nothing beats monolith design latency.
 
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Io Magnesso

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Jun 12, 2025
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X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.
I don't know how Intel's dllc will be implemented...
3D Stack for There are two types: Micro Bonp and Hybrid Bonding.
Well, there are several ways to implement it.
Clock frequency limits will depend on the implementation method
Rather than saying that the foveros packaging technology is the cause I think Intel's L3 cache has a low degree of perfection, or the completeness of cache coherence is poor.
 
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Io Magnesso

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Jun 12, 2025
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Hydrogen bomb is fusion triggered by a small fission bomb.
You can see that the sun is active with hydrogen, but... At present, it is difficult to elicit direct nuclear fusion reactions with human technology.
We need a large-scale facility
 

HurleyBird

Platinum Member
Apr 22, 2003
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There is no need for a 240MB additional cache in a consumer environment

Not when you already have a decisive lead in gaming.

But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure.

Seems pretty unlikely.

And I'd much rather have v-cache on both CCDs than 2x on one and 0x on the other. The frequency hit is small enough now that I'd have preferred AMD to have done this with Zen 5, but 2x v-cache likely hits the frequency hard enough that you wouldn't want to run both CCDs that way.
 

adroc_thurston

Diamond Member
Jul 2, 2023
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But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure
If vidya wanted 2-hi SRAM slabs, you would've gotten them with Zen3.
 

Thunder 57

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Aug 19, 2007
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Not when you already have a decisive lead in gaming.

But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure.

Seems pretty unlikely.

And I'd much rather have v-cache on both CCDs than 2x on one and 0x on the other. The frequency hit is small enough now that I'd have preferred AMD to have done this with Zen 5, but 2x v-cache likely hits the frequency hard enough that you wouldn't want to run both CCDs that way.

There would still be the problem of inter-CCD latency that way.
 

DrMrLordX

Lifer
Apr 27, 2000
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Can we get back to Zen 6 ?
But but THE FUTURE IS FUSION see it all ties together.
It was fixed in lunar lake. that one is 52 cycles.
What's the L3 like in Arrow Lake-S? Chips and Cheese has it at around 80 cycles:


Unfortunately, a longer ring bus and higher L3 capacity translate to higher latency. L3 load-to-use latency on Arrow Lake is north of 80 cycles from a P-Core, compared to about 52 cycles on Lunar Lake. The cycle count penalty is high enough that Arrow Lake’s actual L3 latency is higher than Lunar Lake’s, even though Arrow Lake runs at higher clocks.