Question Zen 6 Speculation Thread

[Josh128]

sorry to put your hopes down but Intel has a bLLC variant without having to limit themselves to X3D frequency limitations they would have other issue though

X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.

 

[511]

X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.

ofc it is it's just the limit is higher now also regarding the expensive part they can charge a premium if it has best gaming perf as for higher latency than x3D that's not necessary if anything nothing beats monolith design latency.

 

[adroc_thurston]

Intel has a bLLC variant without having to limit themselves to X3D frequency limitations they would have other issue though

Their L3 is also dogpoopoo.

 

[CouncilorIrissa]

ofc it is it's just the limit is higher now also regarding the expensive part they can charge a premium if it has best gaming perf as for higher latency than x3D that's not necessary if anything nothing beats monolith design latency.

They would need to fix the 84-cycle L3 first. That's Bulldozer level numbers.

 

[Io Magnesso]

X3D is no longer frequency limited. bLLC, if not a 3D stack of some sort, will be prohibitively expensive and probably higher latency. If its monolithic, it wont be sold to consumers at all, most likely.

I don't know how Intel's dllc will be implemented...
3D Stack for There are two types: Micro Bonp and Hybrid Bonding.
Well, there are several ways to implement it.
Clock frequency limits will depend on the implementation method
Rather than saying that the foveros packaging technology is the cause I think Intel's L3 cache has a low degree of perfection, or the completeness of cache coherence is poor.

 

[Win2012R2]

There are two types: Micro Bomb and Hybrid Bonding

Hydrogen surely 🙄

 

[511]

They would need to fix the 84-cycle L3 first. That's Bulldozer level numbers.

Yeah they need to fix that dogs### it was fine in RPL/ADL

Their L3 is also dogpoopoo.

Yes ARLs L3 has to be the worst L3

 

[Io Magnesso]

Hydrogen surely 🙄

Oops, I wanted to call it Micro Bump

 

[511]

Oops, I wanted to call it Micro Bump

you could have edited it

Hydrogen surely 🙄

also a miniature sun with Hydrogen Bomb

 

[Schmide]

also a miniature sun with Hydrogen Bomb

Sun is fusion not fission.

 

[Abwx]

Sun is fusion not fission.

Hydrogen bomb is fusion triggered by a small fission bomb.

 

[Io Magnesso]

Hydrogen bomb is fusion triggered by a small fission bomb.

You can see that the sun is active with hydrogen, but... At present, it is difficult to elicit direct nuclear fusion reactions with human technology.
We need a large-scale facility

 

[Markfw]

You can see that the sun is active with hydrogen, but... At present, it is difficult to elicit direct nuclear fusion reactions with human technology.
We need a large-scale facility

Can we get back to Zen 6 ?

 

[Io Magnesso]

Can we get back to Zen 6 ?

Well, of course, I was originally made a toy because I made a typo.
I am so sorry

 

[Io Magnesso]

There is no need for a 240MB additional cache in a consumer environment

 

[HurleyBird]

There is no need for a 240MB additional cache in a consumer environment

Not when you already have a decisive lead in gaming.

But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure.

Seems pretty unlikely.

And I'd much rather have v-cache on both CCDs than 2x on one and 0x on the other. The frequency hit is small enough now that I'd have preferred AMD to have done this with Zen 5, but 2x v-cache likely hits the frequency hard enough that you wouldn't want to run both CCDs that way.

 

[adroc_thurston]

But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure

If vidya wanted 2-hi SRAM slabs, you would've gotten them with Zen3.

 

[Tuna-Fish]

If vidya wanted 2-hi SRAM slabs, you would've gotten them with Zen3.

In zen3, the slab is between the heatsink and the compute, vidya probably doesn't want the frequency regression.

 

[Thunder 57]

Not when you already have a decisive lead in gaming.

But if NL is unexpectedly strong in gaming, and games still respond well enough to the additional cache versus further clock speed regression (I'd expect large diminishing returns though), so that you can solidify the gaming crown by stacking another cache chiplet, then sure.

Seems pretty unlikely.

And I'd much rather have v-cache on both CCDs than 2x on one and 0x on the other. The frequency hit is small enough now that I'd have preferred AMD to have done this with Zen 5, but 2x v-cache likely hits the frequency hard enough that you wouldn't want to run both CCDs that way.

There would still be the problem of inter-CCD latency that way.

 

[msj10]

They would need to fix the 84-cycle L3 first. That's Bulldozer level numbers.

It was fixed in lunar lake. that one is 52 cycles.

 

[adroc_thurston]

In zen3, the slab is between the heatsink and the compute, vidya probably doesn't want the frequency regression.

Beyond irrelevant, no V$ part was ever thermally limited.
D2D voltage, OTOH.

 

[DrMrLordX]

Can we get back to Zen 6 ?

But but THE FUTURE IS FUSION see it all ties together.

It was fixed in lunar lake. that one is 52 cycles.

What's the L3 like in Arrow Lake-S? Chips and Cheese has it at around 80 cycles:

Examining Intel's Arrow Lake, at the System Level

Arrow Lake is the codename for Intel's newest generation of high performance desktop CPUs.

chipsandcheese.com

Unfortunately, a longer ring bus and higher L3 capacity translate to higher latency. L3 load-to-use latency on Arrow Lake is north of 80 cycles from a P-Core, compared to about 52 cycles on Lunar Lake. The cycle count penalty is high enough that Arrow Lake’s actual L3 latency is higher than Lunar Lake’s, even though Arrow Lake runs at higher clocks.

 

[CouncilorIrissa]

It was fixed in lunar lake. that one is 52 cycles

Well duh, it has 4 ring-stops and not 12, thrice as small and is in general an entirely different thing.

 

[msj10]

Well duh, it has 4 ring-stops and not 12, thrice as small and is in general an entirely different thing.

lol go tell that to meteor lake with its 75 cycle L3 and 8 ring stops. LNL L3 clearly has more improvements than just "muh less ring stops"

 

[adroc_thurston]

L3 clearly has more improvements than just "muh less ring stops"

It is just muh less ring stops.