Question Zen 6 Speculation Thread

[Win2012R2]

That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.

Why not make them all X3D?

Costs of integration that is good enough for $400 retail product should be far more affordable than doing 48 MB SRAM on N2, plus a chance to increase L1/L2

 

[Josh128]

Why not make them all X3D?

Costs of integration that is good enough for $400 retail product should be far more affordable than doing 48 MB SRAM on N2, plus a chance to increase L1/L2

Price x production complexity x lower yields

 

[511]

Intel is doing the thing with DMR talking L3/IMC in Base tile with DMR/CWF

 

[Win2012R2]

Price x production complexity x lower yields

How do you explain high volume of 9800X3Ds sold for peanuts compared to server versions on per core basis? Clearly yields are good enough.

Punting off L3 to separately produced cheap silicon seems logical way to do it, only question whether it's Zen 6 or later versions, given that they've moved it to the bottom already, so clocks won't be badly affected (and they are low for servers anyway), then Zen 6 sounds like the one to do it.

N2 finally gets some extra SRAM scaling, why waste it on L3 when one can make much needed increase in L1 and L2? Only question when, maybe too much risk for Zen 6 as it's new node, new transistor, but who knows - winner takes it all.

 

[marees]

RDNA 5 WONT be late 2025 lol.

rdna 5 would be q1 27 if we account for the 2 year cadence

As per previously leaked AMD roadmaps it is H2 2026

 

[DavidC1]

Why not make them all X3D?

In addition to what others have said there's also the factor of not being able to price it at premium when it becomes a common part.

 

[Win2012R2]

it becomes a common part.

They all become super duper premium parts - N2 + larger L1/L2 + 3D cache = $$$

 

[Kepler_L2]

Wait a sec how are they going to cram 32 Zen 6 C core without increasing the area cause N3E to N2 is 15% and I can easily bet the core area is going to increase by a lot more than this.

Because SP7 is larger?

 

[jpiniero]

Why would they go to 32 cores when they could just put more dies?

 

[511]

Because SP7 is larger?

They have a new socket .than it makes sense

 

[Kepler_L2]

Why would they go to 32 cores when they could just put more dies?

Easier to design.

 

[adroc_thurston]

Why would they go to 32 cores when they could just put more dies?

You want less NUCA domains, not more.

Why not make them all X3D?

Not enough SoIC wafer starts in the world for that.

Easier to design.

Not really you just want the least amount of NUCA domains possible, especially for cloud parts.

 

[inquiss]

Whatever they use for 3D versions - just move whole L3 cache to the bottom, that should free up space in chiplet.


Why much later? Took them a few months to launch 9800X3D and zero reason they could not have done it at launch as it should have been.

My guess is that servers is #1 goal for them, hyperscalers will certainly be getting them way ahead of launch

Because adding the stacked L3 takes time... Obviously. Like, let's say the chiplet without the stacking can be made at time A, and stacking the L3 takes extra manufacturing steps, the time for that let's say is X. Since we all agree X is non 0, and it's not a few weeks, then they would have to artificially delay the launch of the non x3D chips to launch X3D at the same time. Why do that? X3D will always come later.

 

[inquiss]

That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.

I don't think this is happening, but why does what you're saying have to be the case? We've heard that 2hi stacks is a possibility here. What if one stack is standard and 2 stacks is the addition of extra cache?

Capacity is the answer but technically possible. Feels like that capacity could be built for console chips then AMD can dip into that later, but consoles need to be cheap...

 

[OneEng2]

What 32c/64t part are you talking about? What in this thread, or from elsewhere, makes you think that exists?

Sperate question ...N2 is relatively expensive, what part from desktop, server and laptop would you want to come out first?

Theoretical Zen 6 EPYC CCD on N2.

Good question. From a strategic point of view, I might pick high end desktop with the theory being this is lower volume while yields improve.

He means the 32c server chiplet with Zen 6 Dense. But I think that should be much smaller than 200mm2.

Zen 5c Turin was 84.5mm2 on N3E. I expect that N2 would be ~20% more dense than N3E. So double the cores -> 169 and take off 20% -> 135mm2. So you are right. Quite a bit smaller than 200mm2. Even if more logic is added to Zen 6, it would likely weigh in around 150mm2 ish.

Wait a sec how are they going to cram 32 Zen 6 C core without increasing the area cause N3E to N2 is 15% and I can easily bet the core area is going to increase by a lot more than this.

See above. I used 20%, but the numbers would still be close.

The 16C Zen 5 Chiplet in N3E is ~82mm2 big. Now you get N2 and a smaller PHY for the interconnect to the IOD. So it could be very well the case, that we land at ~150mm2 or so for 32C. Maybe even less.

Agree.

But wasn't speculated, that Zen 6 gets a new socket with 16ch DDR and therefore a bigger socket as well?

Yes. I am guessing quite a bit bigger as they are looking to put so many DDR channels on it. Additionally, I hear the socket power limit is being raised quite a bit as well.

That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.

Agree.

 

[adroc_thurston]

So double the cores -> 169 and take off 20% -> 135mm2. So you are right. Quite a bit smaller than 200mm2. Even if more logic is added to Zen 6, it would likely weigh in around 150mm2 ish.

That's really not what it is man.

 

[Hulk]

That's really not what it is man.

So what is it then because obviously you know so why hold back on us?

He was just doing some napkin math.

 

[LightningZ71]

It only makes sense that it's eventually coming where they start designing certain CCDs with no L3 at all. I wouldn't be at all shocked if Zen7 CCDs had larger L1 and L2 with no L3 at all and all of them were produced with a healthy slab of stacked L3 for DC applications. Consumer might get a half implementation of things with smaller L2, the mobile 2MB of L3 per core and have the option of having stacked L3. Lower SKUs could be stuff like 6 and 8 core chips with full L3 but no stacked and higher SKUs could be things like 10, 12, or even 16 if they get larger, but all with the stacked cache.

 

[adroc_thurston]

It only makes sense that it's eventually coming where they start designing certain CCDs with no L3 at all. I wouldn't be at all shocked if Zen7 CCDs had larger L1 and L2 with no L3 at all and all of them were produced with a healthy slab of stacked L3 for DC applications. Consumer might get a half implementation of things with smaller L2, the mobile 2MB of L3 per core and have the option of having stacked L3. Lower SKUs could be stuff like 6 and 8 core chips with full L3 but no stacked and higher SKUs could be things like 10, 12, or even 16 if they get larger, but all with the stacked cache.

You're so close man. So damn close.

 

[dr1337]

You're so close man. So damn close.

This just sounds like cope.

 

[basix]

For standard devices it does not make sense to remove the L3$. At least not yet. 32MByte of L3$ are ~15mm2 big on Zen 5. With halfed L3$ per core it goes down to 8mm2 or roughly 1mm2 per core. So is it worth to produce a 120mm2 Die with no L3$ but an additional bottom L3$-Die and SoIC? Or just manufacture a bit bigger 150mm2 Die? I think the latter is more R&D and cost effective.

The same for the smaller 12/16C Die with 4MByte L3$ per core. I mean 20/25mm2 of additional area for a 60/75mm2 Die is probably worth it compared to the hassle of an additional Die and 3D-Stacking. The bottom Die costs money as well. Die CCD needs to be cooled.

This might look different for Zen 7, who knows. But even there I have the feeling that removing L3$-Cells entirely from the CCD is not yet here to come to fruition.

 

[Win2012R2]

X3D will always come later.

They can announce it during launch to be available in X months, how about that? And start pre-orders immediately. Then people have certainty.

Also Apple prepares tens of millions of iPhones for launch - somehow they can do it, and it's far more effort than put 1000 chips into trays and off you go.

 

[511]

SRAM bit cell scaling has been dead for few years only N3B had scaling but it was so bad they reverted it back.
The cost to put L3 on between N5 and N2 is a big increase so it makes sense to use HB with N4P as the base die with N2 but the question remains when are we going to see it.

 

[Josh128]

This just sounds like cope.

Or sarcasm. AT has no idea what Zen 7 is going to be.

 

[Thunder 57]

Or sarcasm. AT has no idea what Zen 7 is going to be.

Of course he doesn't. I don't get why some people think of him as a prophet.