Question Zen 6 Speculation Thread

[Thunder 57]

Yeah but... 12 Zen6 cores or 6 Zen6 + 6 Zen6c cores or variations of those ?

Why to early to say but I'm guessing 6 + 6 if the "Zen 6 desktop will use laptop style chips" rumor is true.

 

[Win2012R2]

I'm guessing 6 + 6

It's going to suck for desktop, especially for games for which at least 8 very good highly clocked cores are essential. They'll have to have 12 proper cores for servers and that will have to be a desktop part too. We could see some interesting binning where a few suboptimal cores will be disabled to create very highly clocked 8-10 cores, yum.

 

[DrMrLordX]

It's going to suck for desktop, especially for games for which at least 8 very good highly clocked cores are essential. They'll have to have 12 proper cores for servers and that will have to be a desktop part too. We could see some interesting binning where a few suboptimal cores will be disabled to create very highly clocked 8-10 cores, yum.

Allegedly, Zen6 desktop won't share silicon with workstation/server parts anymore.

 

[adroc_thurston]

laptop style chips

It's client.

It's going to suck for desktop, especially for games for which at least 8 very good highly clocked cores are essential

What's essential is a nice LLC pile.

Allegedly, Zen6 desktop won't share silicon with workstation/server parts anymore.

Yeah, finally. Rickey pile of filthy filthy hacks does the go-away.

 

[Win2012R2]

What's essential is a nice LLC pile.

128 MB slice? Maybe finally it will be as standard and remove 32 MB L3 from main chiplet, should easily make space for 12 proper cores.

Allegedly, Zen6 desktop won't share silicon with workstation/server parts anymore.

Yeah... is it a good thing though? Current model seems to still work well, they just should not cheapen out on IO die, 2x 12 full cores should be good enough for client, just get beefier links to IO to drive that mem bandwidth good.

 

[poke01]

Before this happens, premium laptop makers could hire firmware programmers off of flagship phone makers, so that premium laptops too become able to switch into meltdown mode when the run of a popular benchmark program is detected.

PC laptops have their own problems. x86 laptops perf differs when connected to power and when unplugged.

Macbooks and WoA devices do not do this. When Macbooks were on Intel, they provided the same perf regardless. So this is basically a pissing contest between PC OEMs, AMD and Intel to show bigger numbers.

 

[adroc_thurston]

128 MB slice?

lmao no.

Maybe finally it will be as standard and remove 32 MB L3 from main chiplet

they did that. Just uh, not in client. You guys are too poor for SoIC everywhere.

should easily make space for 12 proper cores.

N3 already offers you that.

Current model seems to still work well

naa.

just get beefier links to IO to drive that mem bandwidth good.

you can already buy that in a few months.

 

[Win2012R2]

you can already buy that in a few months.

You mean Turin or HALO?

 

[StefanR5R]

x86 laptops perf differs when connected to power and when unplugged.

In those cases in which a laptop is configured with a comparably large cooling system but a comparably modest battery, it makes a lot of sense to set different default power limits for components such as CPU and GPU in off-grid vs. on-grid usage. The next consideration is if, or how, to provide options for users to modify such limits.

Vice versa, for laptops which are configured with a smaller cooling system, it may not make sense to set different on-grid and off-grid CPU and GPU power limits.

Allegedly, Zen6 desktop won't share silicon with workstation/server parts anymore.

I wonder whether desktop will still recieve FP/vector throughput oriented core configs. Or maybe not but it'd be compensated by moar coars style configs?

 

[Win2012R2]

I wonder whether desktop will still recieve FP/vector throughput oriented core configs

I can't see them undoing full AVX-512 offered in Zen 5 in later versions - maybe in SOME e-(conomy) cores, perhaps in a form of AVX10/2 256 bits, seems pointless to go down that route now that they have such a great implementation

 

[adroc_thurston]

You mean Turin or HALO?

The latter. Turin has a good IOD but GMI3 is GMI3.

 

[basix]

How would a potential 6+6 Zen 6 client chiplet look like? Something like seen on Strix Point mixed with current desktop flavour?
- Halfed FPU
- Still 4MB L3$ per core

The neat part about that design would be, that Gaming Performance should benefit from the bigger Cache (only 6 "P-Cores" won't be a big issue) and Desktop & Mobile Client use the same CCD.
Server then goes all-in with big FPU, maybe bigger L2$ and some server-only features. And maybe also density optimized because of lower clock speeds of server SKUs?

 

[Thibsie]

I can't see them undoing full AVX-512 offered in Zen 5 in later versions - maybe in SOME e-(conomy) cores, perhaps in a form of AVX10/2 256 bits, seems pointless to go down that route now that they have such a great implementation

Yet, that will happen IMO

 

[Tuna-Fish]

I can't see them undoing full AVX-512 offered in Zen 5 in later versions - maybe in SOME e-(conomy) cores, perhaps in a form of AVX10/2 256 bits, seems pointless to go down that route now that they have such a great implementation

The implementation in Zen4 is also great. It compromises nothing but halved 512-bit throughput. If avx10/2 256 is the new standard, dropping back to the half-width implementation just makes sense.

 

[OneEng2]

Yeah but... 12 Zen6 cores or 6 Zen6 + 6 Zen6c cores or variations of those ?

All of them have SMT and AVX512, so they will be quiet powerful MT beasts.

It's going to suck for desktop, especially for games for which at least 8 very good highly clocked cores are essential. They'll have to have 12 proper cores for servers and that will have to be a desktop part too. We could see some interesting binning where a few suboptimal cores will be disabled to create very highly clocked 8-10 cores, yum.

For games, low latency, high sized cache and high clock speed are all that is important. I suspect we will see an upgraded X3D version for Zen6.

That should satisfy the 1% market of gamers out there.

Allegedly, Zen6 desktop won't share silicon with workstation/server parts anymore.

It doesn't today with Turin D which has a bunch of N3E based 16 core CCDs.

In DC there is little price pressure so no need for economy of scale there.

I expect laptop and desktop to share though. It will be interesting to see what mix of CCDs are used across product lines.

 

[LightningZ71]

I can't see them undoing full AVX-512 offered in Zen 5 in later versions - maybe in SOME e-(conomy) cores, perhaps in a form of AVX10/2 256 bits, seems pointless to go down that route now that they have such a great implementation

They already do that (avx512 half rate in Strix/Kraken).

 

[adroc_thurston]

In DC there is little price pressure so no need for economy of scale there.

This is wrong on so many levels I'm gonna weep.

It doesn't today with Turin D which has a bunch of N3E based 16 core CCDs

Sure does, Granite Ridge still shares the core CCD design with Turin Classic.

 

[Win2012R2]

The latter. Turin has a good IOD but GMI3 is GMI3.

Getting 256 bit memory interface at 10k+ modules on client would be very nice...

 

[Win2012R2]

Yet, that will happen IMO

For some models - yes, but no way they will just go everything desktop to halfed AVX-512, laptops - sure.

If avx10/2 256 is the new standard

Big IF - plus it requires compilation, desktop does not need too many new cores 2x 12 will do good until 2030 easily. It would be real travesty if AMD reverses back just after finally putting AVX-512 on the active development map, with inevitable BIG improvements in memory bandwidth full speed AVX-512 will only benefit, more so than now. I would not be surprised to see a lot of it in video drivers - one would have thought AMD would be pressing their own CPU advantage in this respect, and Nvidia would have to follow.

They already do that (avx512 half rate in Strix/Kraken).

Yes, but they are also providing full speed desktop chips - obviously for thin and light laptops half throughput implementation is more than ok

 

[adroc_thurston]

Getting 256 bit memory interface at 10k+ modules on client would be very nice...

You're not getting that either. Double wide stuff is squarely for -halo.

 

[LightningZ71]

But that's the thing... Client is unifying. With limited main memory throughput, full AVX512 throughput is hamstrung for more than a few cores. If they are putting even more cores in a CCX, keeping full 512 is counterintuitive. The only reason we see it on desktop is due to the shared CCXs with server/DC.

I fully expect to see the Strix implementation carry forward on client CCDs. It will help with clock speeds, it will help keep the cores more compact, and it just makes sense for the environment it's used in. As long as it is logically complete for AVX512 or 10.x, it'll be more than fine.

The full implementation in desktop Zen5 is not showing much improvement over Zen4 where it's tested in any practical, non synthetic way. Check the distributed computing sub here, they tested it and found the improvement to be nearly non-existent where there was any memory constraints at all, which was most of the time.

 

[Win2012R2]

This future sucks, I want me full speed AVX-512!!!

You're not getting that either. Double wide stuff is squarely for -halo.

Well, at least we should be able to get support for 10k+ sticks, +50% on mem bandwidth would be helpful

 

[MS_AT]

The full implementation in desktop Zen5 is not showing much improvement over Zen4 where it's tested in any practical, non synthetic way.

I am counting nearly 90% improvement in throughput bound scenarios and up to 40% improvement in memory bound scenarios on my toy code, you could argue it is synthetic though as I am not using it in any big project but what it is doing is FFT and that is quite popular thing

It will help with clock speeds, it will help keep the cores more compact, and it just makes sense for the environment it's used in

Well, AVX10/256 will be worse than AVX512 ala Zen4, as you will emit twice as much instructions in the frontend to do the same thing. Zen4 was actually shown to clock bit higher with AVX512 than AVX2. But its definitely better for Intel as it allows them to use E-cores with it.

Plus AVX10/256 will be near term as useless as AVX512 seeing how hard it is for AVX2 to gain traction. People are still opposing AVX2 so we are years from widespread adoption of AVX10/256.

What I am trying to say that to keep AVX512 vs AVX512 half-rate vs AVX10/256 is not an easy decision.

 

[Win2012R2]

AVX512 vs AVX512 half-rate vs AVX10/256

If they must cut then AVX512 half-rate is far better option - does not require compile, who knows maybe whole AVX10 may not even be supported by AMD, would be far better if they supported APX instead as priority

 

[Tuna-Fish]

who knows maybe whole AVX10 may not even be supported by AMD,

AVX10.1/256 is AVX512VL without the 512-bit registers. That is, AMD already implements it, it's a subset of AVX512.