So .... we call it "Ryzenburst"?
Clocking higher to raise ST performance is a horrible architectural decision. History has certainly shown this in spades.
Apart from the fact that APU_Fusion was obviously joking:
If it's done by sacrificing IPC like Netburst and Bulldozer did, then sure, but that's not what AMD will be doing.
Zen6 will simply be another Zen4, widening some bottlenecks, phys design optimizations + leveraging faster transistors for notably higher clocks at same power.
If done right, increasing clockspeed is the most reliable way to improve performance, because it's the only thing every type of workload benefits from.
I would rather see more performance at lower clocks and better PPA in the transistors.
That's harder to get right than clockspeed increases, though.
AMD somewhat tried with Zen5 (~30% more core transistors, ~11% more IPC in most workloads).
Intel tried with Sunny Cove (~50% more transistors for ~18% more IPC, higher power draw, barely any PPW improvement while ~50% more area).
I keep warning everyone that ARL is severely hobbled by its chip to chip latency.
Not in every workload, and even there it usually loses against the 9800X3D.
Also, all Intel P cores since Ice Lake/Sunny Cove have been hobbled by meh IPC returns for the amount of transistors invested.
They tried to stay ahead of Zen with a brute force approach and throwing transistors at the problem, and now they have inferior real-world IPC per amount of transistors. Or rather, they use far more transistors and power to maintain IPC competitiveness.
That's hobbling them more than c2c latency, so fixing the latter won't fundamentally fix their 'core' issue (pun intended).
And Arctic Wolf will only mitigate it in multi-threading, since its clocks won't be high enough to beat Zen6 yet.
AMD Zen 4->5 same frequency
E core had Frequency bump of +200Mhz with insane IPC
ARM vendors has room to raise frequency which AMD,Intel don't have
Zen4->5 was on a barely improved node, with a ~30% fatter core due to full-rate AXV512/512bit FP pipes and 50% more INT ALUs.
It was a very server-focused design, so hitting 6+ GHz was secondary, as server CPUs don't clock in that range anyway.
With Zen6 on the other hand, the only server-focused aspect is the design of the 32c dense CCD, otherwise it seems to be more about clocks and core count.
And ARL's E core was a shrink from Intel 7 to TSMC N3B, that's like 3 full node jumps by today's standards (Intel 7 ~= TSMC N10, in terms of density and power efficiency).
Also, right now it still has a fundamentally shorter pipeline and worse V/f curve than Zen, let's wait and see how well its PPA advantage holds up when they keep adding transistors for IPC, SMT, increasing pipeline length and adjust the physical design to hit higher frequencies etc. to reach Zen6/7-like ST performance.
Facebook
Twitter