Question Zen 6 Speculation Thread

[adroc_thurston]

Man, that Zen5 IOD must have been a real screwup

It's the Raphael cIOD and it's a server design.

I wonder what they've changed to achieve a 10x lower idle power consumption on Zen6 (or Strix Halo).

Nothing, they're completely unrelated.

 

[Fjodor2001]

Nothing, they're completely unrelated.

So then that’s the change going to Zen6, i.e. completely different IOD base on Zen6 vs Zen5.

Also, why did they use a server IOD on Zen5 DT? Cheap and easy reuse? Why change policy for that on Zen6?

And why does the server focused IOD have to consume 20-30W instead of 2-3W anyway? What’s the benefit in letting it burn 20-30W, e.g. any better perf or lower price?

 

[adroc_thurston]

So then that’s the change going to Zen6, i.e. completely different IOD base on Zen6 vs Zen5.

Yeah not news.

Also, why did they use a server IOD on Zen5 DT? Cheap and easy reuse?

Because their MCP implementation wasn't made for client back then.

Why change policy for that on Zen6?

Client gets more stuff with Z6.

And why does the server focused IOD have to consume 20-30W instead of 2-3W anyway?

Because it has very very different reliability and power management requirements.

What’s the benefit in letting it burn 20-30W, e.g. any better perf or lower price?

Having enough internal fabric links and switches to not have PCIe p2p transfers choke for one.

 

[OneEng2]

I would GUESS that they learned for Strix and EPYC Zen 5 IOD's.

The Zen 6 IOD incorporates that learning and allows for DDR8000 support.

 

[LightningZ71]

There are minimal power saving provisions for CPU idle on the IOD as it's not really a thing in DC. There's no way to completely shut down the CCD and SerDes link to it at idle. Something has to operate as the system monitor. Adding LP cores to the iOd fixes that aspect. There are many other changes, like the CCD link itself, the lithography node, etc

 

[BorisTheBlade82]

So from 20-30W to 2-3W. Man, that Zen5 IOD must have been a real screwup. I wonder what they've changed to achieve a 10x lower idle power consumption on Zen6 (or Strix Halo).

Basically, it is the interconnect and everything belonging to it, as has been said already since the ineption of Zen 2.

 

[adroc_thurston]

Basically, it is the interconnect and everything belonging to it

Oh no, IFOPs are dirt cheap.
cIOD itself has like no power management.

 

[adroc_thurston]

The Zen 6 IOD incorporates that learning and allows for DDR8000 support.

That's just IMC and mem PHY updates.

 

[QuickyDuck]

It's just all for performance at the cost of power.

 

[dacostafilipe]

Oh no, IFOPs are dirt cheap.
cIOD itself has like no power management.

He's right, it's the interconnect.

It's a SERDES and you're able to go some distance between the two. That's how we've always connected the two. And that's a low cost interface, if you will. It is a high bandwidth interface. But that had low-power states that could only take it so far. And you had retraining and latency implications every time the chip went down and came back up and so on. So for an always-on kind of a desktop kind of machine, that seemed like the best interconnect to connect that as we try to build this into an APU. The first thing we had to do was to change the interconnect between the two dies. And so the CCD that you see here, the core die that you see here, has a different item. That's the first change.

That's a sea of wires. We use fan out, we're for level fan out in order to connect the two dies. So you get the lower latency, the lower power, it's stateless. So we're able to just connect the data fabric through that connect interface into the CCD. So the first big change between a Granite [Ridge] or a 9950X3D and this Strix Halo is the die-to-die interconnect. Low-power, same high bandwidth, 32 bytes per cycle in both directions, lower latency. So everything - and almost instant on-and-off stateless - because it's just a sea of wires going across. So it's a little [bit of a tradeoff] of course, the fabrication technology is more expensive than the one over there [points to a 9950X3D], but it meets the needs of the customer and the fact that it has to be a low power that can actually connect.

Source: https://chipsandcheese.com/p/amds-strix-halo-under-the-hood

 

[maddie]

Does anyone know if the anticipated new IOD in Zen 6 will allow the use of ECC ram, even if not officially supported in non-PRO models?

 

[adroc_thurston]

Does anyone know if the anticipated new IOD in Zen 6 will allow the use of ECC ram

You can do that already.
Just that ECC UDIMMs basically do not exist.

 

[MS_AT]

Does anyone know if the anticipated new IOD in Zen 6 will allow the use of ECC ram, even if not officially supported in non-PRO models?

https://www.techspot.com/review/2907-amd-x870-motherboards/ here they tested the mobos for ECC support. Unless you meant laptops, then these are more limited from what I remember. But for desktop it seems to be up to mobo makers but I don't know the details. Anyway to answer your question, since it's already possible on AM5, I would not expect them to change that

 

[511]

well zen5 CPUs support ECC in the epyc 4005 series so i think it's possible for Z6 to support them as well

 

[LightningZ71]

Just keep in mind, there are several levels of support that have to exist for ECC RAM to work like ECC ram is intended to work. The IMC has to support it, the motherboard has to fully implement the signals, AMD's UEFI firmware wad has to support it for that product, and then the bios manufacturer and motherboard have to actually enable it. Otherwise, you get something that doesn't work at all, or does work, but just as regular memory sticks, or does work, but only reports the errors that it discovers, or, finally, you get fully functional implementations that can correct single bit errors per channel and catch most multi-bit errors.

 

[Doug S]

finally, you get fully functional implementations that can correct single bit errors per channel and catch most multi-bit errors.

And it needs to support a way to deliberately inject ECC errors so that you can verify it is working down to the point where your OS correctly reports it. Silently correcting errors is great but if it isn't telling you it is doing that you don't know you need to replace your DIMM. If you don't know until the first time you get an uncorrectable error and it panics (or just logs that uncorrected error somewhere you may never notice it) it is too late.

 

[Joe NYC]

So from 20-30W to 2-3W. Man, that Zen5 IOD must have been a real screwup. I wonder what they've changed to achieve a 10x lower idle power consumption on Zen6 (or Strix Halo).

These power savings will make a big difference in the 65 Watt parts.

 

[adroc_thurston]

These power savings will make a big difference in the 65 Watt parts.

These aren't relevant.
In luggables, OTOH.

 

[Abwx]

That’s really good.

A whole device use 5.6W for videoplayback, that include 32GB RAM + screen + other circuits, so idle power is very good at barely 2W or so for the APU.

https://www.notebookcheck.net/Asus-ROG-Flow-Z13-GZ302EA-Convertible-Review-AMD-s-Strix-Halo-GPU-is-neck-and-neck-with-the-RTX-4070-Laptop.963266.0.html

 

[igor_kavinski]

And it needs to support a way to deliberately inject ECC errors so that you can verify it is working down to the point where your OS correctly reports it.

Teensy weensy electron gun? Teensy weensy targeted electronic interference generator?

 

[Tuna-Fish]

Teensy weensy electron gun? Teensy weensy targeted electronic interference generator?

... All you need is just a debug feature where it intentionally writes the wrong ECC value for something it writes into memory. I think such things are found in some of the big money big iron stuff.

 

[LightningZ71]

I remember in the x470 days that you could overclock the ram on one of the few boards that supported ecc until it ran well enough to appear stable, but would through ecc errors from time to time.

 

[Doug S]

Teensy weensy electron gun? Teensy weensy targeted electronic interference generator?

Wow, surprised the Anandtech readership is so ignorant when it comes to RAS features. This is standard fare on workstation/server level stuff. Intel and AMD even support it in their consumer memory controllers but it is (unfortunately) typically locked in retail units. IIRC memtest86 even supports it on the units that have it unlocked.

There are also DIMM interposers that allow you to inject errors not only in the data lines but also the control/checksum so you can verify that not just the data but also the commands are properly protected and test the memory controller's scrubbing capability.

 

[RnR_au]

Wow, surprised the Anandtech readership is so ignorant when it comes to RAS features.

I would expect a fair number of garden variety layfolk frequent these parts nowadays. Not many well populated and well managed forums around anymore.

 

[igor_kavinski]

Wow, surprised the Anandtech readership is so ignorant when it comes to RAS features.

No need to blame the entire readership for my ignorance