Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Geddagod]

Structure	Zen 5 vs Zen 4	GLC vs SNC	CYPC vs SKL
Decoder	2 x 4 decoders vs 4 decoders (+100%)	6 vs 4 (+50%)	4 vs 4 (+0%)
Uop Cache	6k* (x2?) vs 6.75K (89%)(+33%)?	4096 vs 2304 (+78%)	2304 vs 1536 (+50%)
Rename/dispatch	8 wide vs 6 wide (+33%)	6 wide vs 5 wide (+20%)	5 wide vs 4 wide (+25%)
ROB	448 vs 320 (+40%)	512 vs 352 (+45%)	352 vs 224 (+57%)
INT reg file	240 vs 224 (+7%)	280 vs 280 (+0%)	280 vs 180 (+56%)
FP reg file	384 vs 192 (+100%)	332 vs 224 (+48%)	224 vs 168 (+33%)

A very, very quick table showing some changes between the archs. Not extensive, not at all.
The uop cache is very weird. So it's 6k entries apparently, vs 6.75k entries of Zen 4, but it's dual ported. So is that 12k vs 6.75k? I don't think so, since it can, at most, dispatch 12 uops per cycle, and Zen 4 can do 9, for a +33% increase, but who knows how many uops per cycle Intel's Uop caches can do... and I did mean this to be only capacity, but that's also not covering the other complexities and changes... but this is also not supposed to be anything extensive... fk it lol.

Structure sizes is a fair point, I guess. Still, Intel somehow needed to expend these xtors on that L2 to move forward, so I feel that AMD did a better job to achieve a comparable jump. They grew the structure sizes, yes, but at a reasonable area cost.

I've always wondered why Intel is continuously expanding it's L2 while other companies seem to be much more conservative in this front. As much as it's an area cost, it also would be a decent static power hit as well, no? Which would hurt especially at lower power levels, which is where Intel struggles the most? Idk, I'm no architect.

The jury is still out on whether Intel have actually managed to hit that 6GHz mark given the recent news, I guess.

🤣

 

[Abwx]

In the slides that compare Zen 5 to Intel s RPL AMD claim 16.8% better perf/Hz for ST in Geekbench, that s quite substancial and shouldnt be far from Spec numbers.

With such an advantage they are good for 24 if not 36 months before releasing their next iteration.

 

[yuri69]

I've always wondered why Intel is continuously expanding it's L2 while other companies seem to be much more conservative in this front. As much as it's an area cost, it also would be a decent static power hit as well, no? Which would hurt especially at lower power levels, which is where Intel struggles the most? Idk, I'm no architect.

The gain brought by doubling the L2 with Zen 4 can be seen in the IPC breakdown. It's nothing to write home about.

 

[DavidC1]

The uop cache is very weird. So it's 6k entries apparently, vs 6.75k entries of Zen 4, but it's dual ported. So is that 12k vs 6.75k? I don't think so, since it can, at most, dispatch 12 uops per cycle, and Zen 4 can do 9, for a +33% increase, but who knows how many uops per cycle Intel's Uop caches can do...

Port is like bandwidth, and it's capacity that takes up space. So it can now be accessed two at a time versus one. 6K is a downgrade, so it's 0.89x.

I've always wondered why Intel is continuously expanding it's L2 while other companies seem to be much more conservative in this front.

Caches are easy way to improve performance? The others require thinking.

 

[PJVol]

Lol, he s telling you the opposite of the truth, i wonder why...

15% decrease is nice.
Just curious though, was it measured for the junction-to-heatspreader path, or including some reference heatsink.

 

[DavidC1]

I find that unconvincing, increasing the L2 isn't really improving PPC that much....

Sure it is, if enhancing the Fetch and BPU for Zen 5 brought just 2%. Caches are actually quite power efficient for their size, and if you need it, it's a great increase in perf/watt because it keeps it away from system memory. If you looked at power distribution for older server processors(Itanium, Power), then 80% is taken up by logic and caches are like 5W.

SRAM isn't a big deal for static power either. It's mostly leakage power that's mostly dependent on process capabilities. If it was power hungry, mobile vendors wouldn't be using it to save great amounts of power. Apple Ax and Lunarlake comes to mind.

We are getting a bit off topic here but I think Icelake's 10nm didn't bring much, if any, perf/watt improvements,

While the actual performance didn't improve, new processes always bring capacitance reduction for power reduction. They were able to go from 24 EU to a 64 EU GPU at the same power, so there was that. So unlike the heydays of Moore's Law, the gains aren't always uniform throughout the blocks on the SoC, and it requires extra work to take advantage of it too.

 

[DavidC1]

I'm not convinced the clustered decode on Zen 5 works well on ST. David Huang got zero from his ST tests, but AMD is saying otherwise. Many times(not always) real tests show results falling short of manufacturer claims, probably because they missed the target. It sounds like it isn't even Tremont level.

The bottom sounds like it's for clustered decode
-From 1x 9-way uop to 2x 6-way uop output.
-2-taken, 2-way TAGE predictor
-L1 fetches 2x32B

Saying it's "6 ALUs" are little bit misleading as saying Skymont doubled to "8 ALUs". Most ALUs added in both architectures are simple ALUs. "BR" on ALUs for Zen 5 means Branch, meaning simpler functions than the multiply for the three. Same for FP. 2 out of the 6 FPUs are Stores, again not much.

Double L1 bandwidth means capabilities of the Load units are doubled.

AMD didn't say anything about increased BTB sizes. Usually, that is the big deal.

 

[Abwx]

15% decrease is nice.
Just curious though, was it measured for the junction-to-heatspreader path, or including some reference heatsink.

That s the thermal resistance between the surface of the die to the external surface of the IHS.

Using Zen 4 as reference at say 95°C for 25°C ambiant, this amount to 70°C delta due to this thermal resistance, with Zen 5 the delta should be 70 x 0.85 = 59.5°C for 84.5°C die temperature.

If by chance they are talking of 15% better thermal conductivity (but why should they?) then the delta would be 61°C and the die temp 86°C instead of the aforementioned 95°C for the 7950X, all this at the same 230W PPT or whatever power that is required to get the 7950X a this temp.

 

[HurleyBird]

I have a feeling that Zen 6 may analogize well with Zen 2, and Zen 7 with Zen 3.

 

[Saylick]

I have a feeling that Zen 6 may analogize well with Zen 2, and Zen 7 with Zen 3.

I can see this. There's a lot of commonality between Zen 2 and Zen 6, namely new packaging, new node, refinement of the prior architecture (which introduced big changes).

 

[scannall]

Ma fault, I should always take AMD marketing for their word. They have surely never lied before!
Top tier cope smh.

I never take marketing slides at face value. From ANY company.

 

[Fjodor2001]

So based on what we know from today's info w.r.t. performance etc, anyone that wants to speculate on pricing?

9950X: ?
9900X: ?
9700X: ?
9660X: ?

Also, bear in mind that rumor is that X3D models will hit the market soon after regular X, and Intel ARL-S soon thereafter.

 

[Hail The Brain Slug]

So based on what we know from today's info w.r.t. performance etc, anyone that wants to speculate on pricing?

9950X: ?
9900X: ?
9700X: ?
9660X: ?

Also, bear in mind that rumor is that X3D models will hit the market soon after regular X, and Intel ARL-S soon thereafter.

My only guess is that 9950X will surprise at $499.

 

[branch_suggestion]

So yeah, lots of new low hanging fruit and the resource gains on the INT side are quite a lot lower than expected.
Will be interesting to see iso-clock benches with neutered FPU Strix vs full FPU GNR.
If the difference is as small overall as I think, then client Z6 might actually adopt the Strix FPU and devote way more area to INT, N3P would allow for some nice gains there along with less area constraints from the new packaging. Or at least allow for different FPU configs depending on if laptop or desktop Medusa.
N2 Dense Z6 on server with the full FPU in 8x32c clusters makes the most sense for Venice.
Big wish for Z6 is 64k L1i but I know that is not gonna happen.

 

[CouncilorIrissa]

So based on what we know from today's info w.r.t. performance etc, anyone that wants to speculate on pricing?

9950X: ?
9900X: ?
9700X: ?
9660X: ?

Also, bear in mind that rumor is that X3D models will hit the market soon after regular X, and Intel ARL-S soon thereafter.

$649, $499, $349, $269 would be my guess.

 

[itsmydamnation]

I'm not convinced the clustered decode on Zen 5 works well on ST. David Huang got zero from his ST tests, but AMD is saying otherwise. Many times(not always) real tests show results falling short of manufacturer claims, probably because they missed the target. It sounds like it isn't even Tremont level.

The bottom sounds like it's for clustered decode
-From 1x 9-way uop to 2x 6-way uop output.
-2-taken, 2-way TAGE predictor
-L1 fetches 2x32B

Saying it's "6 ALUs" are little bit misleading as saying Skymont doubled to "8 ALUs". Most ALUs added in both architectures are simple ALUs. "BR" on ALUs for Zen 5 means Branch, meaning simpler functions than the multiply for the three. Same for FP. 2 out of the 6 FPUs are Stores, again not much.

Double L1 bandwidth means capabilities of the Load units are doubled.

AMD didn't say anything about increased BTB sizes. Usually, that is the big deal.

The hard part is the number of PRF ports , which has increased quite substantially. im sure if they think it mattered that much they would have included more MUL. but its not like MUL a cycle didn't go up. execution easy , data movement hard.

Things i cottoned onto in the talk

1. int PRF hasn't grown in size
2. it sounds like the Load ports are now separate between INT and FP , FP can only Load 2 ops a cycle, but what about 64bit ops destined for the iPRF is it 4 or 2. mike used the phrase those ports are routed to the FPU.
3. that the front end as it stands now is probably a bit spikie , but it to hard to read into is it more or less then Zen4.

 

[Hail The Brain Slug]

$649, $499, $349, $269 would be my guess.

I think those prices are too high. There would be no reason to keep high pricing a secret so close to launch, those prices won't meaningfully eat into the fire sale prices of Zen 4, like the $465 7950X3D, $310 7900X3D, etc.

I would think they're keeping the pricing a secret because it's low enough it will affect Zen 4 sales.

Intel is in such a weak position thanks to the current debacle, competitive pricing out the gate for the new gen would probably turn a lot of heads.

 

[CouncilorIrissa]

I think those prices are too high. There would be no reason to keep high pricing a secret to close to launch, those prices won't meaningfully eat into the fire sale prices of Zen 4, like the $465 7950X3D, $310 7900X3D, etc.

I would think they're keeping the pricing a secret because it's low enough it will affect Zen 4 sales.

That's the entire point. AMD wants to clear the remaining stock of Zen 4 chips first.

Zen 5 will have an undisputed performance crown for a few months. There's no way they would sell the 16C part for anything less than $600, and given their recent history I'd be surprised to see Zen 5 cheaper than Zen 4 launch MSRP by anything more than $50.

AMD wasn't exactly generous with their pricing even with the dumpster fire that was RDNA3. Now imagine a situation when they actually can dictate the terms.

 

[Hail The Brain Slug]

That's the entire point. AMD wants to clear the remaining stock of Zen 4 chips first.

Zen 5 will have an undisputed performance crown for a few months. There's no way they would sell the 16C part for anything less than $600, and given their recent history I'd be surprised to see Zen 5 cheaper than Zen 4 launch MSRP by anything more than $50.

Do you have an alternative explanation as to why pricing being kept a secret so close to launch?

Zen 4 pricing was announced with SKU's 1 month prior to launch
RDNA3 pricing was announced with SKU's 1 month prior to launch
Zen 3 pricing was announced with SKU's 1 month prior to launch
RDNA2 pricing was announced with SKU's 1 month prior to launch

I didn't bother looking back any further, I feel this is enough to establish a pattern.

 

[Josh128]

I think those prices are too high. There would be no reason to keep high pricing a secret to close to launch, those prices won't meaningfully eat into the fire sale prices of Zen 4, like the $465 7950X3D, $310 7900X3D, etc.

I would think they're keeping the pricing a secret because it's low enough it will affect Zen 4 sales.

Intel is in such a weak position thanks to the current debacle, competitive pricing out the gate for the new gen would probably turn a lot of heads.

I'd like to believe they will have some super agressive pricing, but the last time that happened was Zen 2. I think they are in a position to do it, but the corporate push to maximize profits and the uncontrollable urge to capitalize on early adopters will win out. If you consider they are selling a 3 die (plus fillers) 7800X3D for $379 right now, theres basically no reason they couldnt hit with a $329 9700X and still profit.

What the pricing SHOULD be at launch IMO:

$549 - 9950X
$449 - 9900X
$329 - 9700X
$249 - 9600X

What it will probably be:

$649 - 9950X
$499 - 9900X
$379 - 9700X
$299 - 9600X

 

[CouncilorIrissa]

Do you have an alternative explanation as to why pricing being kept a secret so close to launch?

Zen 4 pricing was announced with SKU's 1 month prior to launch
RDNA3 pricing was announced with SKU's 1 month prior to launch
Zen 3 pricing was announced with SKU's 1 month prior to launch
RDNA2 pricing was announced with SKU's 1 month prior to launch

I didn't bother looking back any further, I feel this is enough to establish a pattern.

Waiting for the RPL situation to unfold to decide how much can they gouge consumers.

That and their marketing being a mess in general.

 

[Hail The Brain Slug]

I'd like to believe they will have some super agressive pricing, but the last time that happened was Zen 2. I think they are in a position to do it, but the corporate push to maximize profits and the uncontrollable urge to capitalize on early adopters will win out. If you consider they are selling a 3 die (plus fillers) 7800X3D for $379 right now, theres basically no reason they couldnt hit with a $329 9700X and still profit.

What the pricing SHOULD be at launch IMO:

$549 - 9950X
$449 - 9900X
$329 - 9700X
$249 - 9600X

What it will probably be:

$649 - 9950X
$499 - 9900X
$379 - 9700X
$299 - 9600X

Even though Zen 4 X3D launched 5 months after Zen 4, they didn't change MSRP on any of the Zen 4 SKU's, only retailer discounts. I believe if AMD is going to launch Zen 5 X3D in September as rumored, they will not price up Zen 5 and price cut/aggressively discount only 2 months later. I think they're going to price the Zen 5 SKU's in their final place in the lineup around where the X3D SKU's will land.

If this is the case, 9950X will be priced at or below $600. I am going extremely optimistically with $499 and know that will be unlikely unless I can manifest it hard enough. I've got my copy of The Secret on my desk and I try to re-read parts of it every day.

 

[StefanR5R]

Ma fault, I should always take AMD marketing for their word. They have surely never lied before!

We are two weeks before the review embargo supposedly falls. At this point, marketing slides are unlikely to show projections which the real product will miss. (That's one kind of claims which you perhaps refer to when you talk about having been lied to.) At most I expect that their end note slides gloss over potentially important details of their claims by now. (If this is something which you'd call lying too.)

 

[StefanR5R]

Will be interesting to see iso-clock benches with neutered FPU Strix vs full FPU GNR.

Have AMD themselves mentioned that the FPUs differ?

 

[Mopetar]

At Computex they claimed ZEN5 trashes 14900K. If these Numbers are right, 14900K will be slightly faster instead

All existing 14900K numbers are worthless. I don't care how good they look if the settings required to attain them mean I'll be on my 4th RMA sometime later this year.