Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[LightningZ71]

All Zen5 is showing us so far is that AMD is putting greater comparative focus on the DC/Server side of Zen CCD performance over it's general purpose desktop capabilities. I'm not upset about it as it is still competitive on desktop, but, a full fat AVX-512 and apparently the other changes seem more relevant on server. Still, some of the quotes on here, especially the one about Zen5's front end being enlarged, but the rest of the core not being optimized for it yet, tell me that they were under some sort of not fully expected resource constraint. With the time available between Zen4 and Zen5, I don't think it was time. I still think it was N3B not being ready on time.

Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.

 

[Hitman928]

Desktop is a super-niche, no doubt. However, I'm not sure about the server market.

IMO the largest part are still hyperscalers providing their instances to run classic workloads like web servers, JVM apps, various implementations of microservices, Lambdas, etc. None of those need massive SIMDs.

What needs SIMDs is HPC/scientific workloads and engineering.

AI is better handled by even more specialized accelerators like Intel's AMX. So going for growing markets would be better off with a SKUs featuring some of these...

I'm not involved in the AI server space in any way, but I have talked to a couple of industry people who say that there is a demand for more AI capable general purpose CPUs. It's not nearly as big as for GPUs/accelerators, but it is there and there is significant research happening on getting as much AI performance as possible without having to rely on GPUs/accelerators.

 

[9949asd]

Real r23, only 9% improve than 7950x.

 

[Saylick]

All Zen5 is showing us so far is that AMD is putting greater comparative focus on the DC/Server side of Zen CCD performance over it's general purpose desktop capabilities. I'm not upset about it as it is still competitive on desktop, but, a full fat AVX-512 and apparently the other changes seem more relevant on server. Still, some of the quotes on here, especially the one about Zen5's front end being enlarged, but the rest of the core not being optimized for it yet, tell me that they were under some sort of not fully expected resource constraint. With the time available between Zen4 and Zen5, I don't think it was time. I still think it was N3B not being ready on time.

Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.

I have to agree. I think with a bigger xtor budget, they could've added in more "general purpose IPC". Regarding Zen 6, I think 10% is probably a safe assumption. I wouldn't assume 15% just because I don't foresee big architectural changes. If I were AMD, I would just focus on balancing the structures a little better, addressing corner cases where Zen 5 is weak, and then devote the bulk of the resources to ensure that the new packaging methodology works out of the gate. The IO die is entirely new too, so there's a lot of work that needs to happen there.

 

[yuri69]

Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.

This is possible, although the original roadmap states just double-digits. This means 10 or more %.

Still, Zen 6 is a platform(SoC)-first refinement core. In a similar way the Zen 2 was.

 

[gdansk]

Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.

Sounds like the target is double digit (which is code for 10%).
But who knows, maybe the new process will finally let them hit 6GHz.

 

[CouncilorIrissa]

This is possible, although the original roadmap states just double-digits. This means 10 or more %.

Still, Zen 6 is a platform(SoC)-first refinement core. In a similar way the Zen 2 was.

Double digits? Zen 6 WILL DOMINATE: confirmed to have 99% IPC uplift (cue RGT thumbnail)

 

[igor_kavinski]

can you comment if 43.9K = 230W PBO and the 45K (curve shaper) is also at 230W? Or is it at a higher PPT?

No idea. Don't have those screenshots.

 

[Hail The Brain Slug]

No idea. Don't have those screenshots.

Based on looking at the source article at QuasarZone it looks to be like 42k is fully stock, 43.9k is PBO only (increasing power limit, no curve optimizer), 45.3K is adding curve shaper to that.

The system pictured is on a 240mm NZXT AIO, presumably asetek, so not really a great cooler by any means.

These assumptions mean
Stock : 10.5% uplift
PBO Only: 15.5% uplift (7950X doesn't hit power limit so simply increasing PPT does nothing)
PBO + CO/CS: 15.2% uplift

 

[Saylick]

Double digits? Zen 6 WILL DOMINATE: confirmed to have 99% IPC uplift (cue RGT thumbnail)

RTG: Ladies and Gentlemen, I was told from sources that Zen 6 will have mid-double digits IPC gain. Well, the middle between 10% and 99% is roughly 60%. Zen60% confirmed.

Source (probably): Expect modest gains for Zen 6, like no more than 15% IPC gain.

 

[Hail The Brain Slug]

Interesting for AMD to demo CB R23 in their tech day. I get the idea it shows less than average uplift for Zen 5, and might be strategic to show a less optimistic performance gain, if only by a small amount.

I get the idea CB 2024 uplift would be higher. Would be nice to get some actual figures on that, though. Whoever wins the free benchmark from our ES angel, ask for CB 2024

 

[CouncilorIrissa]

AMD's Zen line has been running 2 leapfrogging teams to produce a pair of cores - a new design and its refinement. Zen 1 + Zen 2; Zen 3 + Zen 4; Zen 5 + Zen 6. So producing an initial core implementing new ideas followed by its close refinement has been the way AMD's been operating since Zen 1.

However, in this case the new design is rather weak:
* Zen 1 scored 52% following low-IPC Family 15h.
* Zen 3 scored 19% with modest core area investment.
* Zen 5 scores 16% following the previous weakest generational IPC gain, blowing the core area quite a bit and being release 21 months after its predecessor at the same time.

It's sad AMD went all-in for AVX512 with Zen 5. Zen 4's approach could have stuck with us for more than a single generation.

I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.

According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.

If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.

 

[CakeMonster]

Z6 will probably be on N3 if its another 18-24 months. How much perf should that bring us by itself?

 

[Josh128]

Based on looking at the source article at QuasarZone it looks to be like 42k is fully stock, 43.9k is PBO only (increasing power limit, no curve optimizer), 45.3K is adding curve shaper to that.

The system pictured is on a 240mm NZXT AIO, presumably asetek, so not really a great cooler by any means.

These assumptions mean
Stock : 10.5% uplift
PBO Only: 15.5% uplift (7950X doesn't hit power limit so simply increasing PPT does nothing)
PBO + CO/CS: 15.2% uplift

I think your percentages are typo'ed, PBO+CO/CS was the highest score, should be the highest % uplift.

 

[Hail The Brain Slug]

I think your percentages are typo'ed, PBO+CO/CS was the highest score, should be the highest % uplift.

No. PBO alone doesn't improve 7950X score without curve optimizer because it's not power limited, so only the 9950X gains here since it continues to scale up with power.

When we introduce CO for 7950X and CS for 9950X, the 7950X begins to make gains again.

Compare my scores for yourself.

7950X Stock: 38k vs. 42k
7950X PBO: 38k (unchanged from stock as mentioned above) vs. 43.9k
7950X PBO + CO: 39.3k vs 45.3k

 

[Saylick]

I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.

According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.

If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.

Also, fwiw, Zen 3 wasn't saddled by having to increase the FP width like Zen 2 was. Zen 3 was an optimization the in purist of senses. I don't recall Zen 3 introducing support for a niche feature or instruction that is known for requiring a lot of xtors.

 

[Timorous]

I have found the 32%. Not Specint though.

 

[Josh128]

No. PBO alone doesn't improve 7950X score without curve optimizer because it's not power limited, so only the 9950X gains here since it continues to scale up with power.

When we introduce CO for 7950X and CS for 9950X, the 7950X begins to make gains again.

Compare my scores for yourself.

7950X Stock: 38k vs. 42k
7950X PBO: 38k (unchanged from stock as mentioned above) vs. 43.9k
7950X PBO + CO: 39.3k vs 45.3k

Oh, I wasnt reading it correctly. I wonder if no-PBO 9950X is just pulling 190W PPT as rumored in WCCFTECH article a week or so ago and you need to enable PBO to get it to hit 230WPPT? Or is the 43.9K and 45.3K figures using more than 230W for the 9950X? Its very murky.

 

[Hail The Brain Slug]

Oh, I wasnt reading it correctly. I wonder if no-PBO 9950X is just pulling 190W PPT as rumored in WCCFTECH article a week or so ago and you need to enable PBO to get it to hit 230WPPT? Or is the 43.9K and 45.3K figures using more than 230W for the 9950X? Its very murky.

Our ES angel has shown that with PBO and uncapped PPT, their ES will exceed 300W. I think it's just scaling well beyond 230W when PBO by itself is enabled, whereas the 7950X lingers around 210-230W even with PPT uncapped.

When I had my 7950X on my custom loop and it was kept cool well below the 95C thermal limit, the highest power I could observe at any PBO + CO configuration was around 240-245W, and it was not sustained, just spikes.

 

[DavidC1]

When every thread has been used ,every thread use just 1*4 decoder(from 2*4 to 1*4),the IPC should decline?

SMT = 1.3x

1.3/2 = 0.65

Zen 5 IPC 35% decline confirmed!

 

[Geddagod]

I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.

According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.

If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.

It appears as if it's AMD's largest jump since OG Zen. It's definitely seems like it's AMD's largest architectural rework since then too. Take that as you will.
SNC to GLC's 72% area jump is large, but with context it becomes a bit more reasonable. The L2 capacity for GLC is much larger. Comparing Willow Cove vs GLC, for example, only nets you a 22% area increase.
I actually do believe Zen 4 to Zen 5 is a SNC to GLC level jump, in terms of buffing structure sizes and such.

 

[yuri69]

I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.

According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.

If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.

That SNC -> GLC jump again... Intel somehow has been pushing a stupidly large L2 cache since WLC. Besides, they hit 6GHz with a minor revision of that core. Zen 4 ate a large portion of that 7nm->5nm transistor budget to run at similar clocks.

Zen 3 was truly the alien. It was the culmination of the Zen core line - balanced 8c CCX. Marketing language like growing trend of CAGR or this one mislead many - myself included. It seemed AMD would triumph with Zen 5. But after Zen 3, there was no low-hanging fruit left.

 

[gaav87]

This slide is so misleading again. 5800X3D doesn't use more than 80W in gaming, so there's a good chance 9700X took more energy in the test. TDP doesn't say anything for gaming workloads. Oh and 7800X3D uses 60W for being 20% faster than 5800X3D.

Oh it does at -30co 2000fclk ~105w in heavy cpu limited games

 

[DavidC1]

That SNC -> GLC jump again... Intel somehow has been pushing a stupidly large L2 cache since WLC. Besides, they hit 6GHz with a minor revision of that core. Zen 4 ate a large portion of that 7nm->5nm transistor budget to run at similar clocks.

Basically smart architects say that if the gains aren't bigger than adding more caches, then don't do it. So with Coves, Intel did.

They may have bought more low hanging fruits with the new decode scheme. Based on the differences between what Mike Clark is saying and what David Huang has got, either there is a difference in what the clustered decode is capable of between mobile vs desktop, or it's not even capable as Tremont and it can only dual decode rarely under ST.

 

[CouncilorIrissa]

It appears as if it's AMD's largest jump since OG Zen. It's definitely seems like it's AMD's largest architectural rework since then too. Take that as you will.
SNC to GLC's 72% area jump is large, but with context it becomes a bit more reasonable. The L2 capacity for GLC is much larger. Comparing Willow Cove vs GLC, for example, only nets you a 22% area increase.
I actually do believe Zen 4 to Zen 5 is a SNC to GLC level jump, in terms of buffing structure sizes and such.

Structure sizes is a fair point, I guess. Still, Intel somehow needed to expend these xtors on that L2 to move forward (maybe the higher-latency and higher capacity L2 made it easier to clock the cores higher? SNC -> WLC was a big clock speed jump, but whether the L2 changes played part in it or was it entirely due to node getting better is a tricky question) so I feel that AMD did a reasonable job to achieve this jump. They grew the structure sizes, yes, but at a reasonable area cost.

That SNC -> GLC jump again... Intel somehow has been pushing a stupidly large L2 cache since WLC. Besides, they hit 6GHz with a minor revision of that core. Zen 4 ate a large portion of that 7nm->5nm transistor budget to run at similar clocks.

The jury is still out on whether Intel have actually managed to hit that 6GHz mark given the recent news, I guess.