Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Ghostsonplanets]

9700X 1-2% faster than 7800X3D on gaming*

*Selection of titles they tested

 

[Hail The Brain Slug]

We already know the score for 9950X, 5ghz all core = 43K~
5.5ghz 47.3K


Guy said that you need decent cooling and PBO to reach 43K.

My 7950X at stock does 5.3 CCD0 and 5.1 CCD1 in CB R23 on a modest air cooler, and is completely thermally limited. You're telling me that the 9950X will be hotter and clock lower despite literally everything indicating the opposite?

OK.

 

[Hail The Brain Slug]

Great perf there! ~29% faster than my 7950X3D @60W PPT with PBO CO tuned:

View attachment 103100

You're not running JEDEC and starving your cores for power. He, for some reason, decided to switch to 4800 JEDEC and 1800 FCLK which opens up several additional watts for the cores.

 

[SolidQ]

Same repeat with zen 4 being marginally faster than 5800x3d?

65 vs 105

 

[Hail The Brain Slug]

View attachment 103099

40W: https://forums.anandtech.com/thread...ranite-ridge-ryzen-9000.2607350/post-41252027

Almost the same core power, I've got a 1.5W advantage at almost 37W vs his 35.5W.

He still can't get away quite yet. The next increase he will certainly take the lead.

 

[Geddagod]

There s dedicated slides for the comparison, think what you want.

"Dedicated slides for the comparison".

 

[MarkPost]

You're not running JEDEC and starving your cores for power. He, for some reason, decided to switch to 4800 JEDEC and 1800 FCLK which opens up several additional watts for the cores.

hmm I see. This is with mem @4800. So ES 9950X is ~18% faster

 

[Abwx]

View attachment 103104
"Dedicated slides for the comparison".

This time they used a 7900XTX, live with it, i mean, you could had find the info but you prefer to post something that has noting to do with the slides i posted, anything else..?..

 

[Hail The Brain Slug]

hmm I see. This is with mem @4800. So ES 9950X is ~18% faster

View attachment 103105

Your SOC power is still way high. Check my run for a 1:1 with his 9950X run.

Page 631 - Discussion - Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Page 631 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[Geddagod]

This time they used a 7900XTX, live with it, i mean, you could had find the info but you prefer to post something that has noting to do with the slides i posted, anything else..?..

No, I'm just pointing out how terrible AMDs marketing slides are, especially when comparing with the competition. People can not trust first part marketing slides. Live with it.

 

[csbin]

good bye N4P

hello N4X

https://twitter.com/x/status/1812856717719515528

 

[Abwx]

You're telling me that the 9950X will be hotter and clock lower despite literally everything indicating the opposite?

OK.

Lol, he s telling you the opposite of the truth, i wonder why...

Ryzen 9000/AI 300: Details zu Zen 5, RDNA 3.5, Zen 6(c) & Zen 7

Ryzen 9000 kommt am 31. Juli. Schon heute gibt es weitere technische Details zu den Desktop-CPUs und Ryzen AI 300 Strix Point für Notebooks.

www.computerbase.de

 

[Geddagod]

good bye N4P

hello N4X

https://twitter.com/x/status/1812856717719515528

Wow that's extremely surprising... are we 100% sure its correct? Lol. I haven't seen it reported elsewhere...

 

[Hail The Brain Slug]

Lol, he s telling you the opposite of the truth, i wonder why...

Ryzen 9000/AI 300: Details zu Zen 5, RDNA 3.5, Zen 6(c) & Zen 7

Ryzen 9000 kommt am 31. Juli. Schon heute gibt es weitere technische Details zu den Desktop-CPUs und Ryzen AI 300 Strix Point für Notebooks.

www.computerbase.de

I've been told in the quoted GN video their 43k cinebench at 5.0 GHz claims are based on a run at 1.35V, where they said "we can run this at 1.1V but we aren't trying to fine-tune yet" or something.

Basically completely meaningless and misleading information.

I will watch the video later to see for myself.

 

[Det0x]

good bye N4P

hello N4X

https://twitter.com/x/status/1812856717719515528

BINGO

Guess thats what the "9950x es leaker" have been trying to show..

 

[Hitman928]

Wow that's extremely surprising... are we 100% sure its correct? Lol. I haven't seen it reported elsewhere...

I have doubt that it is N4X, but it’s possible. I don’t think there’s any chance it’s N4X for Strix though.

 

[tsamolotoff]

I didn't actually lean into the arch-related leaks, but I was under impression that AMD increased functional unit count, but it looks like it remained the same for FPU as compared to Z4? Or am I wrong?

 

[Josh128]

View attachment 103099

40W: https://forums.anandtech.com/thread...ranite-ridge-ryzen-9000.2607350/post-41252027

igor, now that the beans have apparently been spilled, can you comment if 43.9K = 230W PBO and the 45K (curve shaper) is also at 230W? Or is it at a higher PPT?

 

[Hitman928]

BINGO

Guess thats what the "9950x es leaker" have been trying to show..

N4X could give some explanation to the ES leaked results over power sweep. Hopefully we get official confirmation once it launches.

 

[Geddagod]

Wow that's extremely surprising... are we 100% sure its correct? Lol. I haven't seen it reported elsewhere...

According to Cheese, at AMD's breakout rooms, it was reported GNR and STX are N4P, and not N4X.

 

[Saylick]

Zen Daddy LMAO

There’s a ton of interesting information in the Mike Clark interview. C&C put up their own article too: https://chipsandcheese.com/2024/07/...ith-mike-clark-chief-architect-of-zen-at-amd/

Some choice selections:

George Cozma: You know, for a single thread of it, let’s say you’re running a workload that only uses one thread on a given core. Can a single thread take advantage of all of the front-end resources and can it take advantage of both decode clusters and the entirety of the dual ported OP cache?

Mike Clark: The answer is yes, and it’s a great question to ask because I explain SMT to a lot of people, they come in with the notion that we don’t [and] they aren’t able to use all these resources when we’re in single threaded mode, but our design philosophy is that barring a few, very rare microarchitectural exceptions, everything that matters is available in one thread mode. If we imagine we are removing [SMT] it’s not like we’d go shrink anything. There’s nothing to shrink. This is what we need for good, strong single threaded performance. And we’ve already built that.

Mike Clark: We don’t support no op (NOP) fusion. We do have a lot of op fusion that’s similar, we still fuse branches and there’s some other cases that we fuse.

Part of the reason I would say we didn’t put let’s say no op fusion into Zen 5 is that we had that wider dispatch. Zen 1 to Zen 4 had that 6 wide dispatch and 4 ALUs, so getting the most out of that 6-wide dispatch was important and it drove some complexity into the dispatch interface to be able to do that. When looking at having the capability of an 8-wide dispatch and putting no op fusion on top of it, it didn’t really seem to pay off for the complexity because we had that wider dispatch natively. But you may see it come back. Zen 5 is sort of a foundational change to get to that 8-wide dispatch and 6 ALUs. We’re now going to try to optimize that pinch point of the architecture to get more and more out of it and so you know as we move forward, no op fusion is likely to come back as a good leverage of that eight wide dispatch. But for the first generation, we didn’t want to bite off the complexity.

The best nugget of info, imo:

George Cozma: And of course, the most important question that I will ask you of the day, what is your favorite type of cheese?

Mike Clark: I would have to say cheddar.

 

[Hitman928]

According to Cheese, at AMD's breakout rooms, it was reported GNR and STX are N4P, and not N4X.

I think that makes the most sense. Like I said, if GNR were N4X, that could explain some of the behavior we're seeing with the ES sample over power, but I think the most obvious explanation is that it's an ES and the V/F curve just isn't optimized yet.

 

[Abwx]

No, I'm just pointing out how terrible AMDs marketing slides are, especially when comparing with the competition. People can not trust first part marketing slides. Live with it.

Youll see in reviews, for the time these slides rule.

 

[Geddagod]

I didn't actually lean into the arch-related leaks, but I was under impression that AMD increased functional unit count, but it looks like it remained the same for FPU as compared to Z4? Or am I wrong?

The FPU had large changes.
2x vector register file
+1 scheduler (3 vs 2), +50% NSQ
512bit FPU rather than 2x256

 

[Geddagod]

Youll see in reviews, for the time these slides rule.

No, they don't lmao. The cope is wild 💀
All this means is that we still have yet to have any exact info. Just like the situation was before AMD released these slides.