Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Doug S]

5Ghz+ Firestorm has to wait another year.
Physics be damned.

Apple may get there with M6 in 2026 if they maintain their current trajectory frequency-wise.

 

[Jayzen]

Anyway, get some rest everyone. Got a big day tomorrow when Intel falls flat on their face too.
And when Adroc tries to cook up bogus defenses for his big miss today.

 

[Nothingness]

Back of the envelope computations: keeping only integer tests (including video encoding and without AES) that's 14% IPC improvement. Not bad, but yeah nowhere near the 30% which was doubtful given that Zen4 already was a solid core. There's no magic dust, every CPU maker is converging to similar IPC.

If 30% had been a reality it would have been a no brainer for me. But at that level of performance, unless there's a strong efficiency improvement or very strong AVX-512 performance, I'll wait for X3D.

 

[adroc_thurston]

And when Adroc tries to cook up bogus defenses for his big miss today.

But why would I?
This thing doesn't do any warcrimes, it's just kinda mid.

 

[poke01]

I think you're over valuing the ARM and Apple IPC improvements. M4 was like 5% improvement and has been <= 5% for multiple generations now. The latest ARM big core seems to be < 10% though that's still TBD with proper testing. Apple (and ARM to a degree) have mostly been increasing performance through clock gains. Apple is still IPC king because of the lead they had starting several years ago, but IPC increases have not been good as of late.

Geekerwan found SPEC IPC increase to be around 7-8% for M4.

 

[adroc_thurston]

Geekerwan found SPEC IPC increase to be around 7-8% for M4.

People shit on Apple but it’s hard to

Is it iso XCode version or not

 

[yuri69]

MLID got legit AMD slides. Yet, the "30+%" leakerz dismissed them. I mean those having just vague OEM projections at best. Just kek

Btw Cheese was also right - https://chipsandcheese.com/2023/10/08/zen-5s-leaked-slides/

It feels like good old AMD is back. After the Zen 4 stumble and RDNA3 fail we got a classic "grounds up" design. Zen 3 was a pleasant oddity.

 

[NTMBK]

Just woke up, what did I miss? Did we get 350%?

 

[Nothingness]

Geekerwan found SPEC IPC increase to be around 7-8% for M4.

My computations based on Geekerwan data from his first video shows 4.6% IPC increase for M4 vs A17 Pro on SPECint.

 

[adroc_thurston]

After the Zen 4 stumble

?
AMD promised >15% moar 1t and it sure was that.

 

[Joe NYC]

It feels like good old AMD is back. After the Zen 4 stumble and RDNA3 fail we got a classic "grounds up" design. Zen 3 was a pleasant oddity.

I don't think Zen 4 was a stumble as a CPU. Only the platform was a stumble when it launched. Overpriced mobos, chipset confusopoly, DDR5 still on the high side, and PC cycle was about to collapse due to inflated inventories.

It all started to correct itself at the time of 7800x3d release.

 

[gdansk]

MLID got legit AMD slides. Yet, the "30+%" leakerz dismissed them. I mean those having just vague OEM projections at best. Just kek

Btw Cheese was also right - https://chipsandcheese.com/2023/10/08/zen-5s-leaked-slides/

It feels like good old AMD is back. After the Zen 4 stumble and RDNA3 fail we got a classic "grounds up" design. Zen 3 was a pleasant oddity.

It's 3% less in IPC from Zen 3. I don't consider that a big miss personally, especially since IPC gets harder to extract.
But the actual problems are as follows:
1. Some people built a hype train, as usual
2. Clock rate didn't increase. Power TBD.
3. It wasn't a 16 month fast follow-up like Zen 3

 

[poke01]

My computations based on Geekerwan data from his first video shows 4.6% IPC increase for M4 vs A17 Pro on SPECint.

M4 is biggest jump since M1. Apple is having trouble as well, they seemed to hit a IPC wall.

 

[JustViewing]

Yeah, kind of wonder what Mike Clark was on about when talking Zen5, idk, two years+ ago. It’s almost like someone made him take a big cut to the Zen4- Zen5 xtor budget increase.

Engineers gets more exited about architecture than actual performance.

 

[Gideon]

Not an MLID slide. I was the one that convinced Adored not to do a video on it, because the IPC number was lower than expected. My fault for accidentally giving MLID more credibility.
View attachment 100291

Tje most telling part of this slide is the missed schedule. We'd supposed to have Zen 6 by now.

And that's also AMDs biggest weakness. 10-15% every ~7 quarters will not cut it against the current competition. They need to get back to 14-15 months or take bigger risks

 

[adroc_thurston]

Tje most telling part of this slide is the missed schedule. We'd supposed to have Zen 6 by now.

That's not how you read the slide.

 

[itsmydamnation]

The post mortem will be interesting, is the frontend not as bigly as we thought? PRFi or rob sizes smaller then expected? Not a large enough jump in prefetch / predict? If rob >512 and decode a complete rework then I will say zen5 is bulldozer tier execution, they just are in a much better place before hand and made far better architectural choices.

 

[Jan Olšan]

I think they mean Zen 5 still hasn't reached Firestorm IPC.

The post I reacted didn't talk about that at all though...

And the 9950X will probably be behind a 10W iPad in day-to-day tasks because it didn't achieve that nor did it push clock rates higher. Although I guess it is a fair bit cheaper...

Well yeah, heavy pro workflows in Geekbench inside fridge is something AMD won't touch Apple in. I doubt they can even do it. Unless it's some slaughterhouse refrigerator with power mains in...

 

[Timorous]

Zen5 X3D may need to release sooner than claimed so I guess that's an upside.

 

[Saylick]

I saw this get posted on Xitter by HighYield... STX, is that you?

 

[Jan Olšan]

The post mortem will be interesting, is the frontend not as bigly as we thought? PRFi or rob sizes smaller then expected? Not a large enough jump in prefetch / predict? If rob >512 and decode a complete rework then I will say zen5 is bulldozer tier execution, they just are in a much better place before hand and made far better architectural choices.

If it is below targets, it's likely the good old chicken bits, new bottlenecks discovered too late and going to get fixed later, generally stuff panning out below expectations, or not as above "expectations" as actually expected (hoped for).

Zen1-4 mostly panned out on the optimistic side I suppose, maybe Zen 5 was merely a bit less lucky (bigger task / more ambitious?). Something like gen1 Zen not working with the planned 12cycle L2 latency at first, but maybe in more places and less visible than that.

That can still be made up in later generations?

 

[JustViewing]

Now is it okay to ask for more than 16 Cores in desktop?

 

[poke01]

https://twitter.com/x/status/1797496910737252744

AMD and Intel need to clamp ms

I saw this get posted on Xitter by HighYield... STX, is that you?
View attachment 100296

its so pretty.

 

[SolidQ]

Now is it okay to ask for more than 16 Cores in desktop?

isn't that going to Zen6 32Cores?

 

[adroc_thurston]

isn't that going to Zen6 32Cores?

No.
But boy Zen6 CCDs are server.