Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Hitman928]

That's total power consumption you are trying to show in the table.

If your firmware power management is whack at higher power, chances are that it might be the same at lower power.

Which is my interpretation of the MSI claw results.

Under load, the SoC power consumption is by far the dominant factor (unless you have a dGPU loaded). Every power related test they have shows the Asus is allowing the MTL chip to consume more power over time than the MSI laptop. That doesn't mean the firmware is bad or causing issues for SoC performance, it's just how MSI configured it. Once you restrict MTL down to 25W (or especially below) the performance is bad (comparatively) and Arc in actual games performs much worse than it does in benchmarks. We have multiple reviews of multiple different samples all showing this.

 

[Abwx]

You'll need to check with an optometrist - your eyes are failing - when you cannot see that it is clearly stated in the reviews what power levels the models run at.

They do not state everything, look at the graphs of actually measured power comsumption with Furmark, that s the GPU power comsumption under GPU tests, be it Furmark or 3DMark, the difference in the TS score is perfectly in line with the power difference.

 

[APU_Fusion]

We back to Zen5 crushing arrowlake. Wooohoo, I am so glad arrowlake will crush zen 5 because that means’s lower higher prices for us all! Zen 5 > arrowlake > zen 5 ftw

 

[uzzi38]

The MSI handheld having performance issues and the MSI laptop needing twice the power to achieve the same benchmark results as other OEMs doesn't make you pause to think that MSI might be the culprit?

I literally just posted proof that it's not using twice the power in actual games, much less synthetic benchmarks like what you're suggesting.

Stop wasting my time with your cope. This is an issue Intel has literally acknowledged and said they'd release a patch for months ago, and have still been unable to do so.

 

[FlameTail]

What do you guys think?

 

[adroc_thurston]

What do you guys think?

strix clears

 

[Ghostsonplanets]

View attachment 96268
What do you guys think?

Performance: Strix Point (15 - 45W)

Middle of the road between Performance and battery life: Snap X Elite (10 - 45W)

Battery champion: LNL (9 - 30W)

 

[adroc_thurston]

oh yeah about battery life heh. huh. haha. yea.

 

[FlameTail]

strix clears

I recall you admitted that X Elite will have an advantage in efficiency when it comes to fabric power/idle power. So Strix doesn't win in that aspect, no?

 

[adroc_thurston]

I recall you admitted that X Elite will have an advantage in efficiency when it comes to fabric power/idle power

Many ways to skin a cat.

So Strix doesn't win in that aspect, no?

Wins in some, loses in some others.
It'll be some real good fun. real fun.

 

[Ghostsonplanets]

oh yeah about battery life heh. huh. haha. yea.

This is a cryptic as it can get, but let me guess: Both Intel and AMD will offer a huge leap in perf/W and battery life with Strix and LNL, with next-gen x86 laptops being able to comfortably get 8 working hours of battery life and making Snap X Elite efficiency advantage a wash?

 

[adroc_thurston]

and making Snap X Elite efficiency advantage a wash?

Dunno if a wash but yeah, shouldn't be a big delta worst case. LNL was expected, really, Strix is a suprise tho.
Basically the biggest WoA shill point gone poof.

 

[Glo.]

I think, this will be the last generation in which any CPU will be able to work without System cache.

If the rumors are true about Zen 5 - it'll require STUPID amounts of memory bandwidth. Zen 6 will only increase requirements for it. So system level cache will become a must have, and potentially - we will need 256 bit buses on mainstream platforms, even.

 

[adroc_thurston]

If the rumors are true about Zen 5 - it'll require STUPID amounts of memory bandwidth.

Did you really say that when Turin-D stuffs 192 of those things on almost the same memsetup as Genoa?

So system level cache will become a must have, and potentially

They're neat but not mandatory.

we will need 256 bit buses on mainstream platforms, even.

Literally never happening.

 

[gdansk]

Did you really say that when Turin-D stuffs 192 of those things on almost the same memsetup as Genoa?

Isn't it using 25% faster memory?

 

[adroc_thurston]

Isn't it using 25% faster memory?

25% faster memory for 100% more cores that are a bit faster each.
Works out surprisingly well, too, lmao.

 

[poke01]

Basically the biggest WoA shill point gone poof.

I mean Windows will always be married to x86, the slim chance was there but in those year Qualcomm half-***ed with puny chips that couldn’t even run Java minecraft.

Qualcomm should have done this seriously 8 years ago. Now it’s too late. Just cause it worked for Apple doesn’t it’s gonna work for WoA.

So if AMD and Intel managed M1 levels of standby and efficiency I don’t see how Qualcomm takes off. Only saving grace it’s coming 4 months early.

 

[igor_kavinski]

I don’t see how Qualcomm takes off.

They probably won't due to their pricing. But this paves the way for other ARM chips to eat into the marketshare of Chromebooks/netbooks and cheap laptops based on the Intel Atom family and Core i3. Mediatek and Rockchip have a good window of opportunity.

 

[adroc_thurston]

Qualcomm should have done this seriously 8 years ago. Now it’s too late. Just cause it worked for Apple doesn’t it’s gonna work for WoA

QC problem is that they don't understand PCs.
They had an ideal netbook chip and did nothing with it and now they have a performance part that runs no software.
Fantastic.

So if AMD and Intel managed M1 levels of standby and efficiency I don’t see how Qualcomm takes off.

Apple will be ahead as long as everyone else has no real LITTLE.

Mediatek and Rockchip have a good window of opportunity.

Sonoma Valley says hello!
Write your obituaries.

 

[igor_kavinski]

now they have a performance part that runs no software.

What do you mean? WoA can run almost all x86 software in emulation mode, no?

 

[FlameTail]

Apple will be ahead as long as everyone else has no real LITTLE.

Look at how scary efficient Apple's E-core is.

 

[adroc_thurston]

WoA can run almost all x86 software in emulation mode, no?

That's very slow and it can't do anything about AVX+ extensions.
Plus there will be piles of compatability issues with legacy stuff.

Look at how scary efficient Apple's E-core is.

A5xx power at 3 times the perf will never be not funny.

 

[igor_kavinski]

That's very slow and it can't do anything about AVX+ extensions.

So any software with AVX+ instructions refuses to run?

 

[Ghostsonplanets]

Sonoma Valley says hello!
Write your obituaries.

Sonoma is the 4C/8T Z5C + 4 CU RDNA 3.5 Mendoccino successor, right?

I'd say AMD needs to price Sonoma competitively though. Mendoccino currently competes with RPL 282 (Though that's a backhand compliment towards Intel as they basically slashed margins on 282 and flooded the channel).

I'm guessing the rumored SF4+/4LPP+ manufacturing process for Sonoma will alleviate margins for AMD and allow them to offer it at a lower price due to Samsung wafers being cheaper. And Intel also won't have anything as competitive as Sonoma in the budget space by 2025/2026 due to their tiled design approach being inherently costly and RPL 282 being too outdated by then, so it's fair game for AMD.

 

[adroc_thurston]

So any software with AVX+ instructions refuses to run?

Most have SSE fallbacks but again, performance.
You're selling a performance part with no software to use it.

Sonoma is the 4C/8T Z5C + 4 CU RDNA 3.5 Mendoccino successor, right?

dunno the iGP but yes on CPU.

Mendoccino currently competes with RPL 282 (Though that's a backhand compliment towards Intel as they basically slashed margins on 282 and flooded the channel).

282 FLOOOOOOOOOOOOD was a one-off, Intel can't do it with future parts since costs bite.

I'm guessing the rumored SF4+/4LPP+ manufacturing process for Sonoma will alleviate margins for AMD and allow them to offer it at a lower price due to Samsung wafers being cheaper.

SF4X. The HPC finfet SS node.
Correct observations otherwise.