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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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igor_kavinski said:
videocardz.com

AMD CEO to keynote at Computex 2024 on June 3rd, Zen5 incoming? - VideoCardz.com

AMD CEO Dr. Lisa Su will deliver Computex 2024 opening keynote TAITRA, the organization behind Computex has announced today that AMD CEO Dr. Lisa Su will deliver the opening keynote on June 3rd this year. AMD’s keynote will be the first, but not the only, keynote. Computex will kick off on June...
videocardz.com videocardz.com

We possibly have a date!
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Which is -5 to 40+ days of the actual date. 😎
 
FlameTail said:
The first keynote?

That sounds significant.
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Yeah.

The only reason I'm not completely sure it's about Zen5 is that the entire rest of this year's Computex seems to be 100% about AI so it would also make sense for AMD to talk a lot about their AI stuff there. (But hey, Zen branch predictors use perceptrons so they are technically AI (at least as long as you are very willing to stretch the definition until it nearly breaks)).
 
All links, images, etc. must be accompanied by your own commentary.
Okp9wfuwtsPF2VZSte1upRqqAXvJsIEAhS2Nk8VgUNc.jpg

The Zen 5 rumor mill circle.
 
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Amusing. Most of the time it just shows either it's fake or people just don't know how to calculate projections.
But let's be game and make some quick analysis.
If it's a product of clockspeed and IPC then 40% isn't necessarily much. Leaks suggest it could go up to 6GHz. Technically possible since it seems to me ~6.1GHz is the limit for N4 that could be run & sold safely. So we get 5% for clockspeed at most (over 7950x), hence, 1.4/1.05=1.33 or 33% IPC. Assuming it's a max. outlier like those charts given in the past for Zen3 & Zen4 it would be ~2x higher than the actual average. So at worst it's actually just ~16% IPC. Looks like ordinary track record.
So I still think 20% is most reasonable and likely average at best.
 
DisEnchantment said:
View attachment 94376

Wait, is Family A0 --> Zen 6 or some typo?


Update:
This looks like a custom core/family probably
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The only case for this in relationship to Zen5 is:
Family 0Ah 00h-0Fh => Sonoma Valley (Samsung 4nm SF4 Compact 1-fin Lib :: https://ieeexplore.ieee.org/document/9830184 )

Family A0 -> Decimal 160, do to it being a 0.01, I think the A0h is potentially wrong. It is likely to be instead 0Ah -> Decimal 10. It might be that they copied over Bergamo's A0h. As leaping from 00h~1Fh space beyond 20h-9Fh space to A0h is a massive shift. Family 17h Model 160/A0h is Mendocino. However, it's PMC doesn't have tokens for schedulers instead being reserved only. So, it is definitely a quick Bergamo paste where it's A0h potentially replaced 0Ah.

1Ah = Zen5 High Performance cores
0Ah = Zen5 Low Power cores

Zen4's PMC EX Dispatch has tokens for four schedulers. Which Zen4 has:
zen4tokens.jpg

While this design has tokens for two schedulers one for ALU tokens and one for AGU tokens. Which will make it like Bobcat and Jaguar:
lowpower.jpeg

Most of it is basically 1:1 with Zen4 otherwise.

Integer Scheduler is likely to be paired with 6 ALUs
Address Scheduler is likely to be paired with 4 AGUs
It is generally more power-efficient to have a unified scheduler for low-power.
Should functionally be Zen5 except for low-macro count and be extremely synthesized(extra fast ttm vs hybrid hand-tuned/synthesized HP cores)

Family 15h => First Dense core in same family // Zen4/Zen4c and Zen5/Zen5c keeping same family is caused by this.
Family 10h/11h => First HP/LP cores // Zen5 HighPerf/Dense are same family, but 10h/11h, 15h/14h, and 17h/16h denote that Low-power cores do not share family. Thus, Zen5/5c would be Family 1Ah and the Zen5 low power option would be Family 0Ah.

Further is Zen5/5c is "high complexity" which can only be fabbed at TSMC while Zen5 low power would be "low complexity" thus can be fabbed at Samsung.
 
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adroc_thurston said:
SPECINT rate n isn't a "max outlier".
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Does that mean MT uplift is greater than ST?

Zen 4 does seem to plateau before it hits the TDP max so with a wider core I can see it scaling with more power for longer. I can also see heat density being an issue in ST so I would not be totally surprised if nT scales a bit more than sT.
 
Timorous said:
Does that mean MT uplift is greater than ST?

Zen 4 does seem to plateau before it hits the TDP max so with a wider core I can see it scaling with more power for longer. I can also see heat density being an issue in ST so I would not be totally surprised if nT scales a bit more than sT.
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It usually is.
 
Timorous said:
Does that mean MT uplift is greater than ST?

Zen 4 does seem to plateau before it hits the TDP max so with a wider core I can see it scaling with more power for longer. I can also see heat density being an issue in ST so I would not be totally surprised if nT scales a bit more than sT.
Click to expand...
Nah, I thought the consensus was that ST uplift would be larger than MT uplift.
 
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