Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Doug S]

Doubt.

More likely it will be relegated to servers and Apple Mac platforms that can better benefit and profit from it.

Why do you assume that? If Apple was going to be an early adopter of faster DRAM speeds on the Mac, where are the Macs with LPDDR5X?

 

[DrMrLordX]

But I still think that configurable, user replaceable LPCAMM is the way forward- 256 bits of LPDDR5X should be plenty of bandwidth for any APU that fits in a laptop thermal envelope.

As a desktop end-user, overall I'd agree with you since I like the idea better than having my RAM on-package so I can choose better RAM for better performance (which for me means DDR5 or in the future maybe DDR6, not LPDDR anything). But in the future if I'm forced to pick between something higher-latencly like an LPDDR product or something more DDR5/DDR6-like on-package since the "real" CPUs will be workstation/server only, I might be tempted by M1/M2/M3-like solutions. Especially if the on-package solution gets me significantly lower latency. Of course if they're sticking LPDDR on-package then I'll be screwed either way.

 

[Thunder 57]

She talked of Zen 5 for consumers in her first intervention just before talking of the gaming segment, that s in the first lengthy paragraph, and without providing any date.

Epyc being H2 is much later in the conference, so Zen 5 consumers products launch is not related to the date given for Epyc, that s just a wild speculation
from Paul Acorn, dunno how he managed to get to this flawed assumption.

Paul Alcorn has a bias against AMD IMHO. It shows up in his "Best CPUs" articles. There are some categories that are essentialy duplicates to give Intel an extra win. Then there are stupid things like always giving Intel the win for overclocking, despite requiring the most expensive chipset and a k series CPU. Whereas for AMD you only need a B series chipset and any CPU other than the X3D ones can be overclocked.

 

[Abwx]

That isn't true, in all existing AMD's APUs to this day GPU cluster is directly connected to the fabric. GPU has its own L2 and cannot utilize L3 which is part of CPU cluster. See https://chipsandcheese.com/2023/09/16/hot-chips-2023-amds-phoenix-soc/

I really hope that non-Halo Strix Point has either beefed up capacity of L2 or that AMD finally decouples L3 from CPU cluster and transforms it into a SLC from topology point of view. I believe it would also bring a benefit of reduced power consumption.

That s not really the point, how much is the CPU cache filled with datas to drive the GPU.?.
Because if it didnt matter X3D CPUs would gain nothing with their bigger cache.

Paul Alcorn has a bias against AMD IMHO. It shows up in his "Best CPUs" articles. There are some categories that are essentialy duplicates to give Intel an extra win. Then there are stupid things like always giving Intel the win for overclocking, despite requiring the most expensive chipset and a k series CPU. Whereas for AMD you only need a B series chipset and any CPU other than the X3D ones can be overclocked.

I know about the guy, that s why i pointed that his speech cant be taken at face value, it s like he has a big chunk of intel stocks bought at a loss.

 

[Philste]

that s just a wild speculation
from Paul Acorn, dunno how he managed to get to this flawed assumption.

Paul Alcorn has a bias against AMD IMHO

Biased or not, what he wrote wasn't that Lisa Su said something. He wrote 5 hours after the earnings call, that an AMD Rep JUST confirmed that Desktop is H2. It's not that uncommon that companies give out some bits like this, when getting asked by the press.

I can even Leak something more: Volker Rißka of Computerbase wrote in the forum that AMD tild him at the AI Event in early December that they will launch something new at Computex.

My guess is that this was always planned to be ZEN5 DT, Computex presentation with Launch/availability in Mid/late July, 22 months after ZEN4.

 

[eek2121]

Biased or not, what he wrote wasn't that Lisa Su said something. He wrote 5 hours after the earnings call, that an AMD Rep JUST confirmed that Desktop is H2. It's not that uncommon that companies give out some bits like this, when getting asked by the press.

I can even Leak something more: Volker Rißka of Computerbase wrote in the forum that AMD tild him at the AI Event in early December that they will launch something new at Computex.

My guess is that this was always planned to be ZEN5 DT, Computex presentation with Launch/availability in Mid/late July, 22 months after ZEN4.

For desktop specifically, My thought, based on all the leaks, statements, etc. is that we will get a preview in April, if anything, and a formal launch at Computex.

I’ve no idea when laptop chips will drop.

Hey if it comes earlier, it will be a surprise.

 

[StefanR5R]

He wrote 5 hours after the earnings call, that an AMD Rep JUST confirmed that Desktop is H2.

Yep, he said on twitter that he was told something by somebody. As far as we know so far, it's not as if he made an interview with a transcript, let alone a vetted transcript. That is, we don't know what was literally asked nor what was literally answered, nor who the answer gave and on what authority. I admit that not quite everybody here cares for details like that.

Edit:
In his tweet, he said nothing about the release date of Granite Ridge, BTW.

 

[Abwx]

Biased or not, what he wrote wasn't that Lisa Su said something. He wrote 5 hours after the earnings call, that an AMD Rep JUST confirmed that Desktop is H2. It's not that uncommon that companies give out some bits like this, when getting asked by the press.

I can even Leak something more: Volker Rißka of Computerbase wrote in the forum that AMD tild him at the AI Event in early December that they will launch something new at Computex.

My guess is that this was always planned to be ZEN5 DT, Computex presentation with Launch/availability in Mid/late July, 22 months after ZEN4.

I would trust computerbase reviewer more than THG one, THG have been dismissive of AMD, just look at their 8600G coverage title where they say that it match a 7 years old dGPU, quite unprofessional and just a blatant downplaying.

 

[Hitman928]

Biased or not, what he wrote wasn't that Lisa Su said something. He wrote 5 hours after the earnings call, that an AMD Rep JUST confirmed that Desktop is H2. It's not that uncommon that companies give out some bits like this, when getting asked by the press.

I can even Leak something more: Volker Rißka of Computerbase wrote in the forum that AMD tild him at the AI Event in early December that they will launch something new at Computex.

My guess is that this was always planned to be ZEN5 DT, Computex presentation with Launch/availability in Mid/late July, 22 months after ZEN4.

It would be uncommon for an unnamed AMD rep to spill a previously undisclosed launch window to a single journalist right after an earnings call where no such info was released. I'm not saying it didn't happen because I obviously wasn't there and we really have no details at all on the conversation, but it would be highly unusual.

 

[Hans Gruber]

You guys need to focus more on the TSMC process that AMD uses for the desktop Zen 5 market. I am assuming that it will be N4 (4nm) which is really 5nm but significantly better efficiency and a performance uptick vs N5 silicon. When and if AMD moves the desktop Zen 5 to 3nm, will they skip the crappy N3 silicon and get the newer more enhanced 3nm TSMC coming out soon. N3 silicon is 10-15% more efficiency than the N4/4N silicon and 20%+ more efficient than the N5 silicon that Zen 4 is based on. N3 offers no performance uplift other than 10-15% better efficiency than N4 and it's much more expensive. I am not bashing TSMC, just pointing out the difficulties Apple ran into being the first 3nm customer. Apple basically cranked up the power for performance gains which offset the efficiency gains 3nm had over the 5nm TSMC silicon. They were expecting a node shrink to provide performance uplift that does not yet exist with 3nm.

Intel has already said that 18A will be 10% more efficient than 20A which is what Arrow Lake will be based on. I am looking down the road a bit and wondering where 20A efficiency land at vs. Zen 5. That is something that most people miss. Intel has true 5nm silicon this time around with Arrow Lake.

It will be very interesting later in 2024 in the CPU market as well as the GPU market simply because of TSMC silicon. People think Nvidia is such a great designer of GPU's because they use the best silicon available. I am have a personal bias in favor of energy efficiency. That's why a Zen 5 on 3nm would be interesting with either a 45W TDP or 65W TDP with 8 cores. Instead of outright performance wins, AMD could score with massive efficiency CPU's with unlocked cores and overclocking at a lower TDP.

 

[SteinFG]

When and if AMD moves the desktop Zen 5 to 3nm,

Only Turin Dense is on 3nm though.

Intel has true 5nm silicon this time around with Arrow Lake.

There's no "true" anything, just compare the chips at this point. And when comparing chips, Phoenix and Meteor are similar in efficiency.

Instead of outright performance wins, AMD could score with massive efficiency CPU's with unlocked cores and overclocking at a lower TDP.

Who the hell thinks "wish my R5 7600 was 45W instead of 65W, and I could overclock it to 65"
Processors should be able reach their reasonable thermal capacity out of the box, otherwise your heatsink won't be utilised fully.

 

[FlameTail]

You guys need to focus more on the TSMC process that AMD uses for the desktop Zen 5 market. I am assuming that it will be N4 (4nm) which is really 5nm but significantly better efficiency and a performance uptick vs N5 silicon. When and if AMD moves the desktop Zen 5 to 3nm, will they skip the crappy N3 silicon and get the newer more enhanced 3nm TSMC coming out soon. N3 silicon is 10-15% more efficiency than the N4/4N silicon and 20%+ more efficient than the N5 silicon that Zen 4 is based on. N3 offers no performance uplift other than 10-15% better efficiency than N4 and it's much more expensive. I am not bashing TSMC, just pointing out the difficulties Apple ran into being the first 3nm customer. Apple basically cranked up the power for performance gains which offset the efficiency gains 3nm had over the 5nm TSMC silicon. They were expecting a node shrink to provide performance uplift that does not yet exist with 3nm.

Intel has already said that 18A will be 10% more efficient than 20A which is what Arrow Lake will be based on. I am looking down the road a bit and wondering where 20A efficiency land at vs. Zen 5. That is something that most people miss. Intel has true 5nm silicon this time around with Arrow Lake.

It will be very interesting later in 2024 in the CPU market as well as the GPU market simply because of TSMC silicon. People think Nvidia is such a great designer of GPU's because they use the best silicon available. I am have a personal bias in favor of energy efficiency. That's why a Zen 5 on 3nm would be interesting with either a 45W TDP or 65W TDP with 8 cores. Instead of outright performance wins, AMD could score with massive efficiency CPU's with unlocked cores and overclocking at a lower TDP.

Zen 5 DT will use N4P, no?

 

[gdansk]

Hans we've gone over this before. Ada isn't better because of Nvidia magically paying for better silicon. RDNA3 is a dud on N4 in Phoenix and on N5 in N31/N32 and on N6 in N33 and on Samsung 4LPP in the Exynos 2400. Four different processes and RDNA3 is a flop on all of them.

Moreover N3B is "crappy" but in reality it generally has better characteristics than N3E except for the cost. N3 variants do not matter for Zen 5 desktop unless N3E Zen 5C makes an appearance in a mixed CCD part.
Finally, these processes are closer together than basically any time in the past.

 

[FlameTail]

Hans we've gone over this before. Ada isn't better because of Nvidia magically paying for better silicon. RDNA3 is a dud on N4 in Phoenix and on N5 in N31/N32 and on N6 in N33 and on Samsung 4LPP in the Exynos 2400. Four different processes and RDNA3 is a flop on all of them.

Now that you mentioned the RDNA3 iGPU in the Exynos 2400, what is all you AMD guys take on it? The chip is now out and there are plenty of reviews and tests. The Exynos 2400 thread is open for discussion.

Moreover N3B is "crappy" but in reality it generally has better characteristics than N3E except for the cost.

You sure? N3E has better performance/efficiency, even if it's slightly more.

 

[Kepler_L2]

You guys need to focus more on the TSMC process that AMD uses for the desktop Zen 5 market. I am assuming that it will be N4 (4nm) which is really 5nm but significantly better efficiency and a performance uptick vs N5 silicon. When and if AMD moves the desktop Zen 5 to 3nm, will they skip the crappy N3 silicon and get the newer more enhanced 3nm TSMC coming out soon. N3 silicon is 10-15% more efficiency than the N4/4N silicon and 20%+ more efficient than the N5 silicon that Zen 4 is based on. N3 offers no performance uplift other than 10-15% better efficiency than N4 and it's much more expensive. I am not bashing TSMC, just pointing out the difficulties Apple ran into being the first 3nm customer. Apple basically cranked up the power for performance gains which offset the efficiency gains 3nm had over the 5nm TSMC silicon. They were expecting a node shrink to provide performance uplift that does not yet exist with 3nm.

Intel has already said that 18A will be 10% more efficient than 20A which is what Arrow Lake will be based on. I am looking down the road a bit and wondering where 20A efficiency land at vs. Zen 5. That is something that most people miss. Intel has true 5nm silicon this time around with Arrow Lake.

It will be very interesting later in 2024 in the CPU market as well as the GPU market simply because of TSMC silicon. People think Nvidia is such a great designer of GPU's because they use the best silicon available. I am have a personal bias in favor of energy efficiency. That's why a Zen 5 on 3nm would be interesting with either a 45W TDP or 65W TDP with 8 cores. Instead of outright performance wins, AMD could score with massive efficiency CPU's with unlocked cores and overclocking at a lower TDP.

We're long past the days of nodes being any decisive factor in performance and efficiency.

 

[gdansk]

Aaaaeeeh. You sure? N3E has better performance/efficiency, even if it's slightly more.

PPW worse. Density better. For Zen 5 dense it could be a good match but the cost never works out. It is not "crappy", it's too costly for what it does.

Also @Hans Gruber, consider that TSMC says N3E is about 18% more performance than N5 and N4P is also about 15% more performance than N5. Is that extra 2.6% really what will make or break Zen 5?

 

[Tigerick]

PPW worse. Density better. For Zen 5 dense it could be a good match but the cost never works out. It is not "crappy", it's too costly for what it does.

Also @Hans Gruber, consider that TSMC says N3E is about 18% more performance than N5 and N4P is also about 15% performance than N5. Is that extra 2.6% really what will make or break Zen 5?

Yeah, N3B's density is better than N3E due to multi-patterning. N3E is cheaper to implement due to single patterning but the density is lower than N3B process.

 

[FlameTail]

PPW worse. Density better. For Zen 5 dense it could be a good match but the cost never works out. It is not "crappy", it's too costly for what it does.

Also @Hans Gruber, consider that TSMC says N3E is about 18% more performance than N5 and N4P is also about 15% more performance than N5. Is that extra 2.6% really what will make or break Zen 5?

 

[Hans Gruber]

Zen 5 DT will use N4P, no?

I think it's fair to say the N3 silicon will be used with the Turin server chips and N4 will be used for the desktop CPU's. Down the road that may change in 2025.

 

[Thibsie]

Paul Alcorn has a bias against AMD IMHO. It shows up in his "Best CPUs" articles. There are some categories that are essentialy duplicates to give Intel an extra win. Then there are stupid things like always giving Intel the win for overclocking, despite requiring the most expensive chipset and a k series CPU. Whereas for AMD you only need a B series chipset and any CPU other than the X3D ones can be overclocked.

Well, he writes for Tom's, what did you expect ?

 

[Fjodor2001]

Does anyone know what the shortest time has been so far between AMD officially announcing the next gen Zen CPU release date for DT, until actual availability?

I'm trying to estimate the expected availability date of Zen5, based on what date we are at now. E.g. if the shortest time is 3 months, if they would announce it today, it would mean availability is beginning of May based on past track record.

 

[Hitman928]

Does anyone know what the shortest time has been so far between AMD officially announcing the next gen Zen CPU release date for DT, until actual availability?

I'm trying to estimate the expected availability date of Zen5, based on what date we are at now. E.g. if the shortest time is 3 months, if they would announce it today, it would mean availability is beginning of May based on past track record.

I don't know for all of them, but for Zen 3 and Zen 4 it was 1 month from announcement to launch.

 

[Fjodor2001]

I don't know for all of them, but for Zen 3 and Zen 4 it was 1 month from announcement to launch.

Wow, much shorter than expected.

Wasn't there any teaser info published earlier either? Or dead silent until 1 month before availability in stores?

I wonder how they managed to keep it secret in that case, because there must have been CPUs in the sales channels much earlier than 1 month before global availability in stores everywhere.

 

[CakeMonster]

We knew what was happening for certain, but I can't remember if that was mainly because of the calendar, Z4 certainly lined up with 24 months after Z3.

 

[Fjodor2001]

We knew what was happening for certain, but I can't remember if that was mainly because of the calendar, Z4 certainly lined up with 24 months after Z3.

How did ”we” know that for certain?

And in that case, do ”we” also know the same for Zen5?