Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[igor_kavinski]

which brings us to LNC...

Is this the official Jim Keller supervised design? Not from IDC?

 

[blackangus]

Is this the official Jim Keller supervised design? Not from IDC?

Did Keller actually get anything done at Intel ? I thought Keller supposedly left because Intel was not really listening to him... but that could be wrong.

 

[adroc_thurston]

Is this the official Jim Keller supervised design?

no.

Not from IDC?

All Intel big cores are IDC (which is the issue).

Did Keller actually get anything done at Intel ? I thought Keller supposedly left because Intel was not really listening to him... but that could be wrong.

He did, but
a) he left for personal reasons prematurely
b) not everyone listened to him since he's an outsider and not Intel 4 lyfer.

 

[igor_kavinski]

All Intel big cores are IDC (which is the issue).

What year is the first non-IDC big core coming?

 

[adroc_thurston]

What year is the first non-IDC big core coming?

never?

 

[JustViewing]

Did Keller actually get anything done at Intel ? I thought Keller supposedly left because Intel was not really listening to him... but that could be wrong.

As I remember, Keller was the one advocating for modular design where each module is developed in separate process. He mentioned that in couple of interviews. So I would assume, meteor lake is Keller's concept.

 

[maddie]

You mean memory bandwidth per core? That was already discussed in previous posts. In short, I don’t think it’ll be a problem for most MT workloads.

Presenting a narrative solution is the starting point, but you have to do the numbers vs crafting a story. A lot of the perpetual motion designs are so created. Fantasy narrative vs real world numbers.

 

[Timmah!]

If you want more than 16c go with threadripper.

Do you really think 2 channels can properly feed more than 16 cores? We see large uplifts with the 64 core TR going from 4 channel to 8 channel so we know 32c would be limited on just 2.

Ok, send money naow! :-D

And yes, regarding 2 channels being enough. For 24C at least, definitely. Whatever uplift would be there with 4-channel TR, it would be not worth the presumed price difference.

 

[TESKATLIPOKA]

Also if the power target is 230W, 32 Zen4 cores can run comfortably within that limit. Even at 125W, 32 core Zen4 is possible without loosing much of single core performance.

Not true and I am not sure why you wrote single core performance, you wanted to say multi core performance, right?
16C32T 7950X manages 37523pts. TPU
So a hypothetical 32C64T should manage 2x more in theory, in reality It will be less because of nonlinear scaling.
And here is how much points manages the mobile version 7950HX at different power limits.

Even with 230W you will lose ~10-13% of nT performance with a 32C Zen4 CPU. Limit It to 125W and you will lose a lot more.

 

[adroc_thurston]

For 24C at least, definitely

If those were atoms, yeah.
Z5c is very mean.
It's designed to cope with membw not growing on the trees but you're still gonna be stretching it in client.

 

[Timmah!]

If those were atoms, yeah.
Z5c is very mean.
It's designed to cope with membw not growing on the trees but you're still gonna be stretching it in client.

Stretching it is acceptable trade-off for say half the price compared to TR :-D

 

[adroc_thurston]

Stretching it is acceptable trade-off for say half the price compared to TR

Ehhh, kinda.
TR still gonna be leaps and bounds up in perf relative to that.
Plus you'll be breaking the segmentation for a vendor that already is in dominant position in DIY DT.

 

[JustViewing]

Even with 230W you will lose ~10-13% of nT performance with a 32C Zen4 CPU. Limit It to 125W and you will lose a lot more.

Same point I was trying to make, a hypothetical 32Core Zen4 core processor will have near double the performance of 16Core 230W Zen4 processor. 125W maybe a stretch for 32 core Zen4, but could be possible for Zen 5. Or at least with 16 Z5+16 Z5c.

 

[moinmoin]

You need faster cores, not more of them.
Let's just quote an eons old article.

In case anybody else wants to read up on that article without wanting to make the effort of searching for it:

by Johan De Gelas on May 1, 2006

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

There's a mismatch between expectations and what it actually is in general.
People expect another Zen3 and not the biggest-most-fundamental-change-since-Zen1.

Which is kinda funny since even without any inside knowledge one can easily deduce following points:

• Zen cores are AMD's single most important IP. Everything else are building blocks to serve it.
• So once AMD has the resources significant ones will be put into Zen core R&D.
• Zen 1 and 3 were ground up core designs, both started when AMD was still fighting against economic adversities like bankruptcy. The process for the next ground up core design, Zen 5, should be free of such worries from the very beginning.
• So with Zen 5, anything else than significantly bigger improvements than every single previous Zen gen would be unexpected and a grande waste of R&D resources.

Show me an iPad that has higher MT performance than 3950X.

I'm positively surprised nobody checked for some silly GB6 wannabe "MT" scores to prove just that.

 

[adroc_thurston]

Which is kinda funny since even without any inside knowledge one can easily deduce following points:

• Zen cores are AMD's single most important IP. Everything else are building blocks to serve it.
• So once AMD has the resources significant ones will be put into Zen core R&D.
• Zen 1 and 3 were ground up core designs, both started when AMD was still fighting against economic adversities like bankruptcy. The process for the next ground up core design, Zen 5, should be free of such worries from the very beginning.
• So with Zen 5, anything else than significantly bigger improvements than every single previous Zen gen would be unexpected and a grande waste of R&D resources.

This isn't even about R&D money but people being allowed to go ham on area budgets since Dense will server cont-sensitive markets anyway.

 

[Thibsie]

Ah, Johan. I miss the guy.
Well, I miss Aceshardware too. Was I in secondary school when I found that goldmine. Was a review of I don't remember what SPARC CPU. Those were the times...

 

[Thibsie]

This isn't even about R&D money but people being allowed to go ham on area budgets since Dense will server cont-sensitive markets anyway.

Mmm I was still a bit let down but prices of their 'cost sensitively platform aka Sienna.
Not cost sensitive at all to me but maybe that's just (cheap) me.

 

[adroc_thurston]

Mmm I was still a bit let down but prices of their 'cost sensitively platform aka Sienna.

Siena is more edge and the pricing for boxes if fine.

Not cost sensitive at all to me but maybe that's just (cheap) me.

The cheaper-cheaper 4ch platform is for Venice so you'll have to wait.

 

[gdansk]

I'm positively surprised nobody checked for some silly GB6 wannabe "MT" scores to prove just that.

Well it wouldn't be in the spirit of the workloads Fjodor was talking about, would it.

 

[dr1337]

Presenting a narrative solution is the starting point, but you have to do the numbers vs crafting a story. A lot of the perpetual motion designs are so created. Fantasy narrative vs real world numbers.

How about this for a narrative: intel has been shipping ddr4/ddr5 supported desktop chips for years now and there has never been a huge difference in MT workloads.

If a 24c CPU doesn't care about having literally twice the bandwidth doing things like blender and premier, I don't see any reason a 32c CPU would take issue especially with DDR5.

 

[Tarkin77]

Granite Ridge in mass production

https://twitter.com/x/status/1746762927980630326

 

[gdansk]

How about this for a narrative: intel has been shipping ddr4/ddr5 supported desktop chips for years now and there has never been a huge difference in MT workloads.

If a 24c CPU doesn't care about having literally twice the bandwidth doing things like blender and premier, I don't see any reason a 32c CPU would take issue especially with DDR5.

It's a 24C CPU with about as much MT performance as a 16C Zen 4 CPU. Why would it need more bandwidth for about equal performance? And there is a difference impacting some workloads more than others, already at that performance level.

I suspect many of the same reasons as to why AMD didn't do a 8 Zen 4 + 16 Zen 4C consumer part will still apply to Zen 5.

 

[StefanR5R]

blender and premier

They are already GPU accelerated. (Hence they don't contribute to a CPU discussion in the first place.)

 

[maddie]

How about this for a narrative: intel has been shipping ddr4/ddr5 supported desktop chips for years now and there has never been a huge difference in MT workloads.

If a 24c CPU doesn't care about having literally twice the bandwidth doing things like blender and premier, I don't see any reason a 32c CPU would take issue especially with DDR5.

A core is a core is a core? It might be better to think in total IPC and how much cache can mitigate trips to main memory for various workloads. We have to remember that per core IPC is also increasing rapidly. Additional cores will compound the bandwidth issue. Actual data has to be analysed for a quality answer.

 

[coercitiv]

All we need is a bandwidth scaling article using Threadrippers in 16 - 64c configs, in dual vs. quad channel. (the 16c can probably be obtained by disabling cores on a 24c SKU, unless AMD is kind to provide PRO SKUs)

I'm sure there's a 0.1‰ chance that Anandtech is already working one such an in-depth topic. /s