Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[DrMrLordX]

All we need is a bandwidth scaling article using Threadrippers in 16 - 64c configs, in dual vs. quad channel. (the 16c can probably be obtained by disabling cores on a 24c SKU, unless AMD is kind to provide PRO SKUs)

I'm sure there's a 0.1‰ chance that Anandtech is already working one such an in-depth topic. /s

AT won't do it, but we have a few TR and EPYC owners here on the forums . . .

 

[Glo.]

one such an in-depth topic. /s

Why did I read "an in-death topic"?

O_O

 

[Ajay]

AT won't do it, but we have a few TR and EPYC owners here on the forums . . .

Yeah, no one left to do in depth analysis like Ian. :-(

Also, I wish I had need of a 32c Threadripper - would be fun to build a beastly machine like the HEDT system of the past.

 

[blackangus]

All we need is a bandwidth scaling article using Threadrippers in 16 - 64c configs, in dual vs. quad channel. (the 16c can probably be obtained by disabling cores on a 24c SKU, unless AMD is kind to provide PRO SKUs)

I'm sure there's a 0.1‰ chance that Anandtech is already working one such an in-depth topic. /s

Ill do it if someone wants to fund me =)

 

[StefanR5R]

All we need is a bandwidth scaling article using Threadrippers in 16 - 64c configs, in dual vs. quad channel. (the 16c can probably be obtained by disabling cores on a 24c SKU, unless AMD is kind to provide PRO SKUs)

EPYC and Threadripper BIOS setups should expose two related options:

• Disable CCDs, in steps of 2.
• Disable cores per CCD, in steps of 1 core/CCD, simultaneously on all CCDs.

As an aside, dual channel vs. quad channel experiments should be done on Zen ≥3. Zen 2's IOD has got disproportional performance issues if there aren't either 4 or 8 channels populated.

Edit, for channel count experiments on Genoa: https://www.servethehome.com/how-to-populate-amd-epyc-9004-genoa-memory-channels/ = which slots to use if not all twelve or twenty-four.

Anyway. Identifying the memory bandwidth requirements of various highly parallel workloads is one thing. Finding reasons for AMD and/or Intel to suddenly sell us workstation and server CPUs at desktop PC per-core price levels will be another thing. However, even as long as AMD or Intel don't do that and as long as the consumer with his or her highly parallel workload without GPGPU alternative doesn't want to cough up the dough for WS/server level prices, nor want to pay rent in the cloud, not all is lost: These consumers most likely can still put this elusive highly parallel hobby workload onto a dirt-cheap Ethernet cluster of PCs.

 

[yottabit]

Do we know if Zen6 will be AM5 or a fresh socket? I’m assuming fresh socket with the rumored changes to IO. Trying to plan if I’ll want to jump to Zen5 from my 5950x or wait it out

 

[adroc_thurston]

Do we know if Zen6 will be AM5 or a fresh socket?

Can go either way.

I’m assuming fresh socket with the rumored changes to IO

The changes are system design and SiP construction and not really I/O at all.

 

[Glo.]

If it will be AM6 - its better that it has DDR6 support.

 

[adroc_thurston]

its better that it has DDR6 support.

Does not. Exist. Outside of server.

 

[maddie]

Here's an article. 1, 2, 4, 8, memory channels and 32, 64 cores tested.

AMD Threadripper PRO Memory Channel Performance Scaling

AMD Threadripper PRO Memory Channel Performance Scaling

Do modern high-end processors really need up to eight memory channels? How is their performance affected if the number of channels is artificially limited?

www.pugetsystems.com

 

[Fjodor2001]

Here's an article. 1, 2, 4, 8, memory channels and 32, 64 cores tested.

AMD Threadripper PRO Memory Channel Performance Scaling

AMD Threadripper PRO Memory Channel Performance Scaling

Do modern high-end processors really need up to eight memory channels? How is their performance affected if the number of channels is artificially limited?

www.pugetsystems.com

Thanks for sharing. Note that it was tested with DDR4 3200 RAM though. And despite that even with 64 cores it could hold up quite well in several of the tests in 2 and 4 channels. There's some performance drop as expected compared to 8 channels of course. But still I think half the cores (32) and twice the memory speed (DDR5 6400) on 2 channels should work fine for a lot of MT workloads. Especially when taking the much lower platform cost for AM5 into consideration.

 

[adroc_thurston]

But still I think half the cores (32)

Those things are a lot meaner than Zen3.
A lot, lot meaner.

 

[Timorous]

Thanks for sharing. Note that it was tested with DDR4 3200 RAM though. And despite that even with 64 cores it could hold up quite well in several of the tests in 2 and 4 channels. There's some performance drop as expected compared to 8 channels of course. But still I think half the cores (32) and twice the memory speed (DDR5 6400) on 2 channels should work fine for a lot of MT workloads. Especially when taking the much lower platform cost for AM5 into consideration.

Zen5 cores are going to be significantly faster than Zen3 cores. I would not be surprised if a 16c Zen 5 9950X machine can match a 32c Zen3 machine meaning it will need double the ram speed just to feed the data to those cores. Even then we saw the 24 core part scaling to 8 channels and it was frequently the case that 24c + 4 channels was faster than 64c + 2 channels so 16c Zen5 will still be held back by 2 channels of DDR5 6400 making more a bit pointless.

I also do not see a reason to offer more. If you do need more mt than what 16 Zen5 cores can offer then chances are you are being paid for it and you should probably run the numbers on a TR system because long term it will pay for itself.

 

[Fjodor2001]

I would not be surprised if a 16c Zen 5 9950X machine can match a 32c Zen3 machine

100% performance increase per core going from Zen3 -> Zen5, really? What do you base that on?

Also, Zen5 may very well have memory controller and other CPU design improvements + more cache, making it less memory bandwidth hungry than Zen3, all else equal.

Even then we saw the 24 core part scaling to 8 channels and it was frequently the case that 24c + 4 channels was faster than 64c + 2 channels so 16c Zen5 will still be held back by 2 channels of DDR5 6400 making more a bit pointless.

Of course, more memory bandwidth is always better. But in several workloads the difference was not that big. And note that we’re talking about twice the amount of cores (64), and half the bandwidth (DDR4 3200). So with 32C and DDR5 6400 you’ll have 4x the memory bandwidth per core compared to that, when using the same number of channels.

 

[Hail The Brain Slug]

100% performance increase per core going from Zen3 -> Zen5, really? What do you base that on?

Also, Zen5 may very well have memory controller and other CPU design improvements + more cache, making it less memory bandwidth hungry than Zen3, all else equal.


Of course, more memory bandwidth is always better. But in several workloads the difference was not that big. And note that we’re talking about twice the amount of cores (64), and half the bandwidth (DDR4 3200). So with 32C and DDR5 6400 you’ll have 4x the memory bandwidth per core compared to that, when using the same number of channels.

7950X enjoys somewhere around a 50% improvement in multicore against a 5950X, stock for stock. A hypothetical 16C zen 5 part would need around 30-35% MT uplift against a 7950X to be in the neighborhood of 2x a 5950x.

 

[Fjodor2001]

7950X enjoys somewhere around a 50% improvement in multicore against a 5950X, stock for stock.

Citation needed. And no cherry picking, but average across multiple types of MT workloads.

 

[Markfw]

Citation needed. And no cherry picking, but average across multiple types of MT workloads.

speaking from experience, if you include avx-512, I see that as very possible. And before my 8 7950x's, I had 6 5950x's, and still have 3 of them. I gave away 2 to family members.

 

[dr1337]

Zen5 cores are going to be significantly faster than Zen3 cores. I would not be surprised if a 16c Zen 5 9950X machine can match a 32c Zen3 machine meaning it will need double the ram speed just to feed the data to those cores.

If (according to sources like OC3D, GN, TS) a 24c CPU from another brand matches a 7950x in MT while having a 1% difference between DDR4 and DDR5, then there is no basis to say memory bandwidth is an issue in the first place. A 24c Zen 4 CPU would be fine on DDR4 and a desktop Zen 5 CPU with 32c let alone 24c would also still be fine on DDR5 for the market segment that its targeting.

7950X enjoys somewhere around a 50% improvement in multicore against a 5950X, stock for stock. A hypothetical 16C zen 5 part would need around 30-35% MT uplift against a 7950X to be in the neighborhood of 2x a 5950x.

The problem is the other poster is assuming that somehow performance and memory bandwidth requirements are 1:1, when they actually are not at all. For a Zen 5 CPU to be bandwidth starved compared to Zen 4, it's going to need a greater than 50% increase in memory bandwidth usage and that implies a lot more than 30% increase in IPC.

It's not like Zen 3 was way more bandwidth sensitive than Zen 2 after all.

speaking from experience, if you include avx-512, I see that as very possible.

And what if you forget about it like 99% of programs do? Science applications like molecular dynamics and crypto hashing definitely depend on BW but even then they require 48c+ for it to matter. Productivity applications like encoding and rendering really don't care as much.

 

[adroc_thurston]

Also, Zen5 may very well have memory controller and other CPU design improvements + more cache, making it less memory bandwidth hungry than Zen3, all else equal.

It's the same cIOD as Raphael and the only bigger cache is L1d (48K now).

 

[Markfw]

And what if you forget about it like 99% of programs do? Science applications like molecular dynamics and crypto hashing definitely depend on BW but even then they require 48c+ for it to matter. Productivity applications like encoding and rendering really don't care as much.

I am saying that if you add a fair amount (5-10%) avx-512 to the benchmark suite, like some place do, then I could see it being 50% faster than Zen 3. Many places ignore that, since Intel does not support avx-512 for desktop.

 

[blackangus]

I just saw this summary of Zen5:
Features touted by AMD:

• New grounds-up microarchitecture
• Enhanced performance and efficiency
• Re-pipelined front-end and wide issue
• Integrated AI and Machine Learning optimizations

What is that last line referring to feature wise?

 

[adroc_thurston]

What is that last line referring to feature wise?

It does bf16 SIMD math faster.

 

[branch_suggestion]

Does not. Exist. Outside of server.

CAMM2 is going to lead to a very fun transition period, I guess this indicates only RDIMM derivatives will exist for DDR6.
Zen5 will remain DIMM only, even Strix Halo unless any laptop OEM wants to do the funny.
Zen6 could support both for all we know, instead of AM6 we might see AM5+ with CAMM2, and you can still run it on standard AM5.
Will be a very interesting period for AMD/Intel to manage across PC, CAMM2 is such a big shift on DT that it might also lead to ATX being replaced by a more elegant solution.
I would be happy if all standards designed in the 20th century would finally die. More CXL features on client PCIe would be welcome.

 

[adroc_thurston]

I guess this indicates only RDIMM derivatives will exist for DDR6.

Yeah that signaling isn't something you can do on DIMMs without register buffering.

Zen5 will remain DIMM only, even Strix Halo unless any laptop OEM wants to do the funny.

-halo is LPDDR-only.

More CXL features on client PCIe would be welcome.

Kinda pointless since CXL holed itself into "switched memory pools" ghetto aka very not useful for client.

 

[yuri69]

I just saw this summary of Zen5:
Features touted by AMD:

• Integrated AI and Machine Learning optimizations

What is that last line referring to feature wise?

AVX-VNNI support and likely improved handling of already supported "AI" instructions.