Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Abwx]

Vanilla Zen6 is all N3p, N2 only for Dense CCD iirc.

Still, they should use a better perf/watt performing process than for Zen 5, there s some usable gain from the process to increase perfs, while Zen 5 should use a good part of its process perf/Watt improvement to compensate for the bigger and inherently lower uarch efficency at isofrequency.

 

[adroc_thurston]

Still, they should use a better perf/watt performing process than for Zen 5

Very very very very very incremental node improvement.

and inherently lower uarch efficency at isofrequency.

Now that's the funny bit, AMD tends to deliver 1:1 IPC/Cdyn.

 

[A///]

Is n2 not when tsmc plans on introducing gaa and backside power delivery?

 

[adroc_thurston]

Is n2 not when tsmc plans on introducing gaa and backside power delivery?

GAA yes, BSPDs are for N2p.

 

[A///]

oops, sorry I made an error. pcie5 came with alderlake, a year after it was finalised by pci sig.

 

[A///]

GAA yes, BSPDs are for N2p.

that should be a fun time to witness whether it's successful and lives up to the hype or it doesn't.

 

[Abwx]

Very very very very very incremental node improvement.

Now that's the funny bit, AMD tends to deliver 1:1 IPC/Cdyn.

I was talking at isoprocess, you cant compensate the bigger transistor count to achieve a higher IPC by reducing Cdyn on a same process, you ll have forcibly to use a process with lower Cdyn, that is, the next node.

For that matter a 5nm fabbed Zen 3 would be more efficient than Zen 4 at same frequency, but not at same throughput.

Of course for a same throughput one can reduce Zen 4 frequency by 12% and hence reduce its power by roughly 25%, wich more than largely compensate for the lower intrinsical efficency, for instance if intrinsical efficency is say 10% lower Zen 4 will still have 8% better throughput at isopower and isoprocess.

 

[Tigerick]

Golden Pig Upgrade pretty much confirmed the specs of Strix Point coming next year.

Hmm, based on total cores with L3 cache improvement and 8WGP (or total 1024 SALU), the die size would be much bigger than 178mm2 of Phoenix Point

 

[TESKATLIPOKA]

Finally, performance comparable to GTX 1650M? 😀

 

[A///]

If the C in Zen meant dense initially what the heck does a zen5d mean?

 

[moinmoin]

If the C in Zen meant dense initially what the heck does a zen5d mean?

c stands for cloud and is essentially the PR name, d is dense and is the unofficial name still often used (maybe even internally at AMD seeing how often it still pops up?).

 

[Exist50]

He/she seems to be implying that Zen 5c and 5d are different cores???

 

[adroc_thurston]

He/she seems to be implying that Zen 5c and 5d are different cores???

No.

 

[A///]

c stands for cloud and is essentially the PR name, d is dense and is the unofficial name still often used (maybe even internally at AMD seeing how often it still pops up?).

I may be missing something but I can't find any data that makes a difference between the C and the D. Both are stripped down traditional cores to pack up to 16 of them on a compute die. If i search against amd's own website with the worse dense it brings up zen4c.

 

[SteinFG]

They probably mean Zen5[C]lassic and Zen5[D]ense

 

[BorisTheBlade82]

Just as @moinmoin said: Zen4c was also mentioned first as Zen4d. Just later on they exchanged the d for a c. So I agree that it is highly likely, that internally they still call the family "dense" and not "cloud".

 

[yuri69]

Should be the same as Zen+ to Zen 2 or from this latter to Zen 3, since Zen 5 is supposed to be a bigger departure from Zen 4 than thoses previous itérations we can expect it to be some sort of pipe cleaner like Zen 1 in its time.

If Zen 5 IPC improvement is substancial comparatively to Zen 4 it would be logical that Zen 6 would bring significantly less IPC uplift, they ll surely focus on perf/Watt with a 2nm node jump.

OTOH *if* those hype claims are true - Zen 5 being a radical departure from the old 4-wide Zen design bringing ~20% IPC & being the last gen on the "2010 packaging tech". Then Zen 6 could still bring a nice IPC gains.

First, a fresh architecture always cuts corners meaning its direct successor has plenty of low-hanging fruit. Second, current Zen 4 and probably Zen 5 too are limited by the current IF architecture - having a completely new one could boost a class of workloads.

Also Intel is gonna keep releasing new stuff every year so in 2026 Zen 6 has to bring a substantial perf boost to compete.

 

[trexfromouterspace]

Now that's the funny bit, AMD tends to deliver 1:1 IPC/Cdyn.

Not happening

 

[adroc_thurston]

Not happening

That's what happened at Zen3 so...

 

[A///]

OTOH *if* those hype claims are true - Zen 5 being a radical departure from the old 4-wide Zen design bringing ~20% IPC & being the last gen on the "2010 packaging tech". Then Zen 6 could still bring a nice IPC gains.

First, a fresh architecture always cuts corners meaning its direct successor has plenty of low-hanging fruit. Second, current Zen 4 and probably Zen 5 too are limited by the current IF architecture - having a completely new one could boost a class of workloads.

Also Intel is gonna keep releasing new stuff every year so in 2026 Zen 6 has to bring a substantial perf boost to compete.

was there not a rumor of amd going 8 wide and intel going even wider earlier in the year or was that all bs?

 

[Abwx]

OTOH *if* those hype claims are true - Zen 5 being a radical departure from the old 4-wide Zen design bringing ~20% IPC & being the last gen on the "2010 packaging tech". Then Zen 6 could still bring a nice IPC gains.

First, a fresh architecture always cuts corners meaning its direct successor has plenty of low-hanging fruit. Second, current Zen 4 and probably Zen 5 too are limited by the current IF architecture - having a completely new one could boost a class of workloads.

Also Intel is gonna keep releasing new stuff every year so in 2026 Zen 6 has to bring a substantial perf boost to compete.

From the tone of Mike Clarck interview Zen 5 should be noticeably above the average level of previous iteration, so 18-20% is possible for Zen 5, but it s likely that Zen 6 will be within the usual uplifts, FTR the average improvement per iteration from Zen to Zen 4 was 13% using Cinebench as metric.

For the time we have not the slightest technically accurate info about the uarch, only that the l1 cache is increased by 25%, the hints given by AMD, re-pipelined front end and wide issue, dont say much without knowing if there s significant changes in the execution engine and LSU, FI if the ALU count is increased to 5 or 6, how much more LS/cycle and width if there s any.

 

[PJVol]

Now that's the funny bit, AMD tends to deliver 1:1 IPC/Cdyn.

Never seen "Cdyn" in AMD tech docs, they always use the term Cac

 

[adroc_thurston]

Never seen "Cdyn" in AMD tech docs, they always use the term Cac

Yea that's Intel lingo.
As I've said, I talk mostly to Intel or near-Intel people.

 

[PJVol]

As for 1:1, I also don't understand how this is possible. This is Cac distribution for heavily optimized 7nm in Zen2 from their slides. 22% is accounted for clock tree and gaters, and that's just the Core

 

[Geddagod]

AMD managed to keep roughly the same clocks at the same voltage while delivering a ~20% IPC uplift (on the same node), which was pretty impressive, with zen 3 vs zen 2.