Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[soresu]

I have no DLSS which would generate this missing information.

Ironically DLSS just hallucinates it anyway 😂

 

[NostaSeronx]

Only if the new "V" models are fabbed on GloFo FDSOI.

The only weird design I have identified is a ultra-high-frequency Zen5 concept. Which pushes the OoO-logic into the front-end with a full-on trace cache. Opting for a ultra-modern ROB-free checkpoint-based retire. Which from the model numbers might go for a 9Fx5(F going into core count for change in max cores) number denotation if the concept launches. Only the UHF and Standard HF designs are appearing on N3=45CPP.

 

[TESKATLIPOKA]

Ironically DLSS just hallucinates it anyway 😂

I think the smoothing effect looks great.

But back to Zen5.
I would like to see a CCD with both standard and dense cores.
Smaller CCD: 4x Zen5 + 4x Zen4/5c
Bigger CCD: 6x Zen5 + 6x Zen4/5c
With this, they can have the full lineup:
CPU 1: 3x Zen5 + 3x Zen4/5c -> 6C12T
CPU 2: 4x Zen5 + 4x Zen4/5c -> 8C16T
CPU 3: 5x Zen5 + 5x Zen4/5c -> 10C20T
CPU 4: 6x Zen5 + 6x Zen4/5c -> 12C24T
CPU 5: 2xCCD 8x Zen5 + 8x Zen4/5c -> 16C32T
CPU 6: 2xCCD 10x Zen5 + 10x Zen4/5c -> 20C40T
CPU 7: 2xCCD 12x Zen5 + 12x Zen4/5c -> 24C48T

If they made only a single CCD then I would go with 4x Zen5 + 6x Zen4/5c instead for a total of 20C40T.

 

[soresu]

But back to Zen5.
I would like to see a CCD with both standard and dense cores.
Smaller CCD: 4x Zen5 + 4x Zen4/5c
Bigger CCD: 6x Zen5 + 6x Zen4/5c
With this, they can have the full lineup:
CPU 1: 3x Zen5 + 3x Zen4/5c -> 6C12T
CPU 2: 4x Zen5 + 4x Zen4/5c -> 8C16T
CPU 3: 5x Zen5 + 5x Zen4/5c -> 10C20T
CPU 4: 6x Zen5 + 6x Zen4/5c -> 12C24T
CPU 5: 2xCCD 8x Zen5 + 8x Zen4/5c -> 16C32T
CPU 6: 2xCCD 10x Zen5 + 10x Zen4/5c -> 20C40T
CPU 7: 2xCCD 12x Zen5 + 12x Zen4/5c -> 24C48T

If they made only a single CCD then I would go with 4x Zen5 + 6x Zen4/5c instead for a total of 20C40T.

Mmmpf.

Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?

Especially if V cache stacking can balance out the L3 difference in the dense CCDs.

 

[TESKATLIPOKA]

Mmmpf.

Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?

Especially if V cache stacking can balance out the L3 difference in the dense CCDs.

In mobile and desktop you would lose a lot of ST performance by using only C cores, that's not something users want.

It would be fine only in server or maybe in ultra low power mobile where low TDP wouldn't allow higher clocks than C cores are capable of at same or better efficiency than standard ones.

 

[LightningZ71]

Mmmpf.

Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?

Especially if V cache stacking can balance out the L3 difference in the dense CCDs.

Stacking the cache requires that you build in vias into the L3 area of the chip. This causes a density hit and would force the C core CCDs to be larger than they currently are. You might see this in the future, but, I doubt it any time soon.

 

[Joe NYC]

I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.

Great minds think alike:

 

[Timorous]

Great minds think alike:

It is the obvious play if AMD want more MT perf in desktop. Even if some people get really confused at the idea

 

[Thibsie]

I don't think this is much of a problem. From a practical standpoint, the lower end of the lineup is targeted towards primarily consumers (gamers, office PCs, etc.). 8 full cores has generally been sufficient for that market. The ones who need more MT performance are content creators and professionals, and it wouldn't be a stretch to upsell them to the higher tiers.

Mmmm with Intel spamming e-cores, it doesn't matter. Back to 'more is better'.
The only problem is price IMO

 

[Thibsie]

Mmmpf.

Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?

Especially if V cache stacking can balance out the L3 difference in the dense CCDs.

But not the frequency deficit.

 

[eek2121]

There could be a mild refresh of the branding for AMD's products that reflects the change in structure and warrants a pricing increase...

8950X 2 X Zen5 CCD 8 cores each, 16/32 Costs $A
8955X 1 X Zen5 CCD, 8 cores 1 X Zen5c CCD 16 cores, 24/48 Costs $A + $75
8900X 2 X Zen5 CCD 6 cores each, 12/24 Costs $B
8905X 1 X Zen5 CCD 6 cores 1 X Zen5c CCD 16 cores, 22/44 Costs $B + $70
8800X 1 X Zen5 CCD, 8 cores, 8/16, Costs $C
8805X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 12 cores (faulty cores) 20/40 Costs $C + $70
8700X 1 X Zen5 CCD 8 cores, reduced power, 8/16 Costs $D
8705X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 8 cores, Reduced power (bad CCX) 16/32 Costs $D + $70
8600X 1 X Zen5 CCD 6 cores, 6/12, Costs $E
8605X 1 X Zen5 CCD 6 cores, 1 X Zen5C CCD 6 cores (bad CCX and a bad core) 12/24 Costs $E + $60

It also allows a new Suffix
8900V 1 X Zen5C CCD, 16 cores, 16/32 Costs $X
8800V 1 X Zen5C CCD, 12 cores, 12/24 Costs $Y
8700V 1 X Zen5C CCD, 8 cores, 8/16 Costs $Z

So, there's a way if the WANT to. They just have to CHOOSE to do it.

And, no, I don't think that they will actually do ANY of the above for the 8000 series...

Because AMD favors margins above all, you are looking at a lot more than a “mild” price increase.

I don’t know the numbers for N5, and I am too lazy to do the math, but on 7nm each CCD costed like $70-$80. The cost has risen since then. For AMD to add a second CCD, you are likely looking at a $150 ($CCD Cost * 1.5 (AMD’s margin)) price difference. While this number ignores the technicals behind binning, I doubt enough binning could be done at this point to cover that amount of money, particularly when the dense chips are in extremely high demand for enterprise. AMD would make less money by putting them on desktop.

 

[eek2121]

Mmmm with Intel spamming e-cores, it doesn't matter. Back to 'more is better'.
The only problem is price IMO

I think a number of folks here have never used a single or dual core system. Shoot, you can even tell the difference between a quad core and 8-core system.

More cores absolutely does help to a point, and also, software tends to chase the hardware, not the other way around. Put high core counts in every user’s hands and the software will adapt and optimize.

Example: Windows defender now uses the GPU and also extra cores. This saves power and lowers CPU power consumption. It would’ve been unheard of for virus scanners to do this a decade ago. Shoot, with all of the hardware changes, defender runs in the background scanning files in realtime and most users don’t even notice. That was impossible in the past.

 

[Abwx]

I don’t know the numbers for N5, and I am too lazy to do the math, but on 7nm each CCD costed like $70-$80.

That would put the waffer at roughly 50k$, wich wasnt the case, cost is rather in the 30$/CCD at the die level.

 

[soresu]

But not the frequency deficit.

Depends on how you look at it.

I'd rather have a 32 core CPU running at 3 Ghz than a 16 core running at 4.5 Ghz ish.

Something tells me that the former would be more efficient too, even with a wider core than Zen4.

 

[Hans Gruber]

Depends on how you look at it.

I'd rather have a 32 core CPU running at 3 Ghz than a 16 core running at 4.5 Ghz ish.

Something tells me that the former would be more efficient too, even with a wider core than Zen4.

Did something tell you running 3ghz with 32 cores vs 16 cores @ 4.5Ghz is a server chip?

 

[Thibsie]

Depends on how you look at it.

I'd rather have a 32 core CPU running at 3 Ghz than a 16 core running at 4.5 Ghz ish.

Something tells me that the former would be more efficient too, even with a wider core than Zen4.

Yeah, of course if we multiply cores at the same time. But those need to be fabbed. Probably a lot less expensive to drive them to higher frequencies (if doable).

 

[soresu]

Did something tell you running 3ghz with 32 cores vs 16 cores @ 4.5Ghz is a server chip?

Almost certainly but my PC desires are seldom realistc 😂

 

[soresu]

Probably a lot less expensive to drive them to higher frequencies (if doable).

If the current formula for Zen4 CCD -> Zen4c CCD holds it's supposed to be only a 10% greater area per die.

So less expensive certainly, but not a lot less expensive until you account for the V$ dies.

 

[TESKATLIPOKA]

Depends on how you look at it.

I'd rather have a 32 core CPU running at 3 Ghz than a 16 core running at 4.5 Ghz ish.

Something tells me that the former would be more efficient too, even with a wider core than Zen4.

Why should I choose only from those options?
I would rather have a combination of both cores, so I will have the best performance regardless of use case.

 

[DrMrLordX]

Why should I choose only from those options?
I would rather have a combination of both cores, so I will have the best performance regardless of use case.

That's a little surprising. For me, I want more high-clockspeed cores wherever possible. 16c is already massive overkill for most non-workstation/server builds, and just adding more cores on top of that with "efficiency" cores seems stupid outside of maybe power-constrained scenarios.

 

[Abwx]

If the current formula for Zen4 CCD -> Zen4c CCD holds it's supposed to be only a 10% greater area per die.

So less expensive certainly, but not a lot less expensive until you account for the V$ dies.

32C/64T would make sense technically speaking, if we look at Computerbase CB R23 tests the 7950X does 38 600 pts at a 205W measured power for their sample, and 30 200 pts@88W, so 4 chiplets in a 32C/64T whould roughly do 60 000 pts@180W.

Thing is that there would be very few buyers for a 1500$ SKU, not counting that it would be in competition with TR and Epyc, although the low count memory channels wouldnt fare well with a lot of apps.

 

[soresu]

That's a little surprising. For me, I want more high-clockspeed cores wherever possible. 16c is already massive overkill for most non-workstation/server builds, and just adding more cores on top of that with "efficiency" cores seems stupid outside of maybe power-constrained scenarios.

Needz core count to maximum - gots to get all the threads for offline 3D rendering 😎

I'd love to see some Bergamo benches for Cinebench/Cycles/Arnold renderers and other CG related tasks like FLIP or MPM sims.

I think there may be a better future for such absurdly parallel DCC tasks when more frameworks exist that support both SYCL/OneAPI and HIP aswell as the popular CUDA - but we are still far from that sadly 😭

I hope that someday everyone might use a framework like OpenSYCL (formerly hipSYCL) which supports all the major API backends - but it's definitely got some ways to go before it has that level of maturity.

 

[DrMrLordX]

Needz core count to maximum - gots to get all the threads for offline 3D rendering 😎

Now you're on more of a workstation workload though. Yes some hobbyists might want moar coarz for 3D rendering, but for "serious" users they'll be picking products like EPYC or Threadripper.

 

[Exist50]

Now you're on more of a workstation workload though. Yes some hobbyists might want moar coarz for 3D rendering, but for "serious" users they'll be picking products like EPYC or Threadripper.

But realistically, other than E-peen, that's what the dual CCD chips are for. Or maybe not so much rendering, but rather things like video/photo editing. It would be a pretty narrow slice of workloads that would benefit from >8c but be disadvantaged by the dense cores.

 

[DrMrLordX]

It would be a pretty narrow slice of workloads that would benefit from >8c but be disadvantaged by the dense cores.

There's always a tradeoff. Cost/power/interconnect penalties etc. AMD has demonstrated the ability to add an extra CCD without paying too high a price for it, other than tacking on a higher MSRP.