Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[jpiniero]

Only remaining question is: but what about gaming laptops. Will the 4+8 design be optimal, or will there need to be another pproach instead?

HX line mainly, especially if it continues to be cheaper than the APU.

 

[uzzi38]

HX line isn't applicable for smaller machines.

Needs to be a third.

 

[SteinFG]

I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).

Just want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.

I'm more interested in the cores: if TR on Siena ever comes out, will it use 64x Zen4c or 32x Zen4? 4-channel or 6-channel ?

 

[SteinFG]

Looked at amd's statement again - seems like Siena TR will not come out:

"Threadripper processors have always been a platform that is defined by leadership performance and capability which enables unlimited creative potential. Examining what our most demanding enthusiasts and content creators value most in the platform has led us to unify the Threadripper and Threadripper PRO product lines. Going forward, the Threadripper platform will now use a single "common infrastructure." This means there will be one set of Threadripper PRO processors to choose from, with one CPU socket and chipset, and every processor will be based on AMD Ryzen Threadripper PRO silicon"

 

[Ajay]

Just want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.

I'm more interested in the cores: if TR on Siena ever comes out, will it use 64x Zen4c or 32x Zen4? 4-channel or 6-channel ?

I’m not familiar with the Siena platform. If you have a link - I’d appreciate you sharing it. Tia

 

[SteinFG]

I’m not familiar with the Siena platform. If you have a link - I’d appreciate you sharing it. Tia

Siena is SP6 socket platform. Pretty much everything that's known:

 

[TESKATLIPOKA]

I'm more interested in the rumored 'Sarlak' variant with up to 40 RDNA3 CUs.

With something that meaty I could probably just ditch my desktop for all but work related use cases.

You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.

Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.

 

[SteinFG]

You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.

Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.

My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.

 

[TESKATLIPOKA]

My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.

For that performance, you don't need Sarlak, even Strix point would be enough.
Series S: 20 CUs @ 1.565 GHz, 4.01 TFLOPS
Even Strix with 16CU would need only 2GHz for comparable raw power.
BW would still be a problem, but at least Strix Point wouldn't cost as much as Sarlak.

It's very likely that Strix will be in the next Asus ROG Ally 2 or some different Chinese brand, but 12C24T is a bit of an overkill.
I personally would make an APU: 4xZen5 + 4xZen5c/Zen4c + 20CU + 48MB LCC + 128-bit GDDR5x.

 

[Joe NYC]

He does say no to different ISAs or different IPCs. So, again, I’m confident that it’s a no for Zen5 and likely no for Zen6. But, as always, we shall see. All bets are off for AM6.

I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.

 

[Joe NYC]

I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).

I seem to recall one version of the rumors that Sienna would have 6 channels of memory.

This, at least, should not be subject to rumors. The Sienna socket is defined, specs are out there, people have answers, but it seems that no one is digging for the answers.

AMD already has enough sockets (not counting legacy) between AM5, SP5 (Genoa), SP6 (Sienna), SH5 (Mi300).

So unlikely that there will be any "enthusiast" level socket. And AMD has always found a way to cripple the Threadripper platform so that it would never be seen as a HEDT platform. We will see if this continues with the next Threadripper on Sienna platform.

The only thing that's left out is the Strix Halo, if it will ever have a socketed version. As I posted above, Strix Halo in AM5 socket, with 4 internal channels and 2 external memory channels would be a very exciting product...

 

[Ajay]

I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.

That sounds like a reasonable interpretation to me.

 

[moinmoin]

I seem to recall one version of the rumors that Sienna would have 6 channels of memory.

That's not the rumour. SP6/Sienna is 6 ch, SP5/Genoa is 12 ch, those are known. Threadripper so far always has been re-using the server platform, but in case of non-Pro with cut channels. So the rumour went with 8 ch and 4 ch, a cut of a third of the respective server channels.

Anyway as @SteinFG mentioned before AMD already publicly announced unifying both Pro and non-Pro before, so an uncut SP6/Sienna based TR seems most likely at this point.

DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR

DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR AMD launched the AMD Ryzen™ Threadripper™ line of disruptive, high performance desktop processors in 2017. Since then, Threadripper processors have quickly become the processor and compute platform of choice for the world’s most...

community.amd.com

 

[SteinFG]

I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.

Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.

The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.

 

[SteinFG]

That's not the rumour. SP6/Sienna is 6 ch, SP5/Genoa is 12 ch, those are known. Threadripper so far always has been re-using the server platform, but in case of non-Pro with cut channels. So the rumour went with 8 ch and 4 ch, a cut of a third of the respective server channels.

Anyway as @SteinFG mentioned before AMD already publicly announced unifying both Pro and non-Pro before, so an uncut SP6/Sienna based TR seems most likely at this point.

DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR

DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR AMD launched the AMD Ryzen™ Threadripper™ line of disruptive, high performance desktop processors in 2017. Since then, Threadripper processors have quickly become the processor and compute platform of choice for the world’s most...

community.amd.com

Siena has 32 zen4/zen5 cores at most (it goes to 64 Zen4C/Zen5C cores but I doubt AMD wants to put low-clock low-cache C cores on threadripper) , even tr 5995wx had more cores and memory channels than this. The most likely scenario is that Threadripper will be on the SP5 socket with 12 memory channels

Edit: can't find the info on how many pcb layers do 12-channel genoa motherboards have. does anyone know? By my guess, it should be like 20, but I think i'm wrong.

 

[soresu]

You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.

Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.

You missed my point entirely, it's about powaaah NUCs 😅

 

[Tuna-Fish]

Siena is SP6 socket platform. Pretty much everything that's known:

In addition, the "why" of Siena, discussed with press afterwards, is to have something that reasonably fits a 1U chassis and into the same set of TDPs that Intel used for a decade, so that customers who want to keep all their infrastructure can replace old server blades 1-to-1.

Also good for everyone who want a server platform, but just don't need anywhere near the capability available on SP5.

 

[eek2121]

Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.

The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.

Except that AMD making everything dual CCD would (excluding the IO die) double the cost of making the chip while they would only be able to make half as many. I don’t think they will consider that route.

 

[SteinFG]

Except that AMD making everything dual CCD would (excluding the IO die) double the cost of making the chip while they would only be able to make half as many. I don’t think they will consider that route.

That's... Exactly what I was saying:

because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.

 

[Ajay]

Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.

The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.

Lol! I wouldn't upgrade my 5900x system on any AM5 based product if that was the case (may not anyway, but that's a budget issue). The main reason I use a 12- core system is that I have VMs running at times that use as many as 6 cores (6c/12t). Though, if the Zen6 HD CCD matched or exceeded the performance of the Zen3 core, which is certainly possible, I would rethink things.

 

[TESKATLIPOKA]

You missed my point entirely, it's about powaaah NUCs 😅

You didn't mention NUCs anywhere, you only said you could ditch your desktop with It.
I have no DLSS which would generate this missing information.

 

[LightningZ71]

There could be a mild refresh of the branding for AMD's products that reflects the change in structure and warrants a pricing increase...

8950X 2 X Zen5 CCD 8 cores each, 16/32 Costs $A
8955X 1 X Zen5 CCD, 8 cores 1 X Zen5c CCD 16 cores, 24/48 Costs $A + $75
8900X 2 X Zen5 CCD 6 cores each, 12/24 Costs $B
8905X 1 X Zen5 CCD 6 cores 1 X Zen5c CCD 16 cores, 22/44 Costs $B + $70
8800X 1 X Zen5 CCD, 8 cores, 8/16, Costs $C
8805X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 12 cores (faulty cores) 20/40 Costs $C + $70
8700X 1 X Zen5 CCD 8 cores, reduced power, 8/16 Costs $D
8705X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 8 cores, Reduced power (bad CCX) 16/32 Costs $D + $70
8600X 1 X Zen5 CCD 6 cores, 6/12, Costs $E
8605X 1 X Zen5 CCD 6 cores, 1 X Zen5C CCD 6 cores (bad CCX and a bad core) 12/24 Costs $E + $60

It also allows a new Suffix
8900V 1 X Zen5C CCD, 16 cores, 16/32 Costs $X
8800V 1 X Zen5C CCD, 12 cores, 12/24 Costs $Y
8700V 1 X Zen5C CCD, 8 cores, 8/16 Costs $Z

So, there's a way if the WANT to. They just have to CHOOSE to do it.

And, no, I don't think that they will actually do ANY of the above for the 8000 series...

 

[SteinFG]

There could be a mild refresh of the branding for AMD's products that reflects the change in structure and warrants a pricing increase...

8950X 2 X Zen5 CCD 8 cores each, 16/32 Costs $A
8955X 1 X Zen5 CCD, 8 cores 1 X Zen5c CCD 16 cores, 24/48 Costs $A + $75
8900X 2 X Zen5 CCD 6 cores each, 12/24 Costs $B
8905X 1 X Zen5 CCD 6 cores 1 X Zen5c CCD 16 cores, 22/44 Costs $B + $70
8800X 1 X Zen5 CCD, 8 cores, 8/16, Costs $C
8805X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 12 cores (faulty cores) 20/40 Costs $C + $70
8700X 1 X Zen5 CCD 8 cores, reduced power, 8/16 Costs $D
8705X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 8 cores, Reduced power (bad CCX) 16/32 Costs $D + $70
8600X 1 X Zen5 CCD 6 cores, 6/12, Costs $E
8605X 1 X Zen5 CCD 6 cores, 1 X Zen5C CCD 6 cores (bad CCX and a bad core) 12/24 Costs $E + $60

It also allows a new Suffix
8900V 1 X Zen5C CCD, 16 cores, 16/32 Costs $X
8800V 1 X Zen5C CCD, 12 cores, 12/24 Costs $Y
8700V 1 X Zen5C CCD, 8 cores, 8/16 Costs $Z

So, there's a way if the WANT to. They just have to CHOOSE to do it.

And, no, I don't think that they will actually do ANY of the above for the 8000 series...

Noooooo, you got bit by Nosta 😭

 

[Thunder 57]

Noooooo, you got bit by Nosta 😭

Only if the new "V" models are fabbed on GloFo FDSOI.

 

[Exist50]

Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.

The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.

I don't think this is much of a problem. From a practical standpoint, the lower end of the lineup is targeted towards primarily consumers (gamers, office PCs, etc.). 8 full cores has generally been sufficient for that market. The ones who need more MT performance are content creators and professionals, and it wouldn't be a stretch to upsell them to the higher tiers.