Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[gdansk]

Who doesn't want Zen 5 to be a behemoth? But after all the AMD hype trains who can believe it without evidence. Fool me 7 times shame on me.

They've done well many times but the expectations get out of control. And it is especially hard to believe when they don't really need the rumored performance to beat their competition. 20% IPC seems possibly more than needed.

 

[adroc_thurston]

Who doesn't want Zen 5 to be a behemoth?

It literally is.
That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.

But after all the AMD hype trains who can believe it without evidence

like what?
They've been dominating the CPU game (server in particular) for like ~4 years already.

And it is especially hard to believe when they don't really need the rumored performance to beat their competition. 20% IPC seems possibly more than needed.

that's not how you design anything lol

 

[moinmoin]

AMD hype trains

What are you talking about? adroc just killed my expectation that AMD finally would increase the link speed (per cycle, I know I know) with Zen 5. I'm seriously bummed here, lol.

That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.

Impeccable reasoning.

 

[adroc_thurston]

Impeccable reasoning.

It's literally why Phoenix, LNC and Zen5 look oddly similar.
Very sus haha (the answer is they all were N3(b) cores originally).

 

[soresu]

Can't spam SRAM, can't scale the frequency anymore so the only choice remains.

Not SRAM, but it won't always be the only player in the game at that latency.

 

[adroc_thurston]

but it won't always be the only player in the game at that latency.

I've been burnt on so many SRAM/DRAM replacement hopiums that I'd rather not say anything like that ever.

So yea, core bloat is the way forward.

 

[exquisitechar]

20% IPC seems possibly more than needed.

In the long run, not really. Intel's big cores after RWC are looking to be really good too.

20% seems like the floor to me given what AMD accomplished with Zen 3 and what Zen 5 is rumored to be.

 

[gdansk]

It literally is.
That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.

like what?

that's not how you design anything lol

It goes way back. People hyped K10 to the moon. Or more recently the claims Zen 2 would be 5GHz. Or bondrewd's misinterpretation of RDNA3.

Sometimes reality does not end up matching unsourced performance projections.

What are you talking about? adroc just killed my expectation that AMD finally would increase the link speed (per cycle, I know I know) with Zen 5. I'm seriously bummed here, lol.

They'll cut it in half if you don't stop talking about it.

 

[adroc_thurston]

Intel's big cores after RWC are looking to be really good too.

They're pretty good but I wonder if they're good enough.

20% seems like the floor to me given what AMD accomplished with Zen 3 and what Zen 5 is rumored to be.

Bingo.

It goes way back. People hyped K10 to the moon

Yea it was a rather solid design TLB bugs aside and in itself is a byproduct of like there dead K9 attempts.

Or more recently the claims Zen 2 would be 5GHz.

Only one dumb youtuber did that.

Or bondrewd's misinterpretation of RDNA3.

RDNA3 still works as well as it should in headless compute.
Still a cursed piece of IP.

Sometimes reality does not end up matching unsourced performance projections.

They're not projections, the Si has sampled and perf targets are now final.

 

[gdansk]

They're not projections, the Si has sampled and perf targets are now final.

That's my bad you had made that clear previously.

 

[soresu]

I've been burnt on so many SRAM/DRAM replacement hopiums that I'd rather not say anything like that ever.

So yea, core bloat is the way forward.

Oh don't get me wrong I've not much hope (especially in DRAMs case - it's a frickin zombie 😂), but if SRAM has run into a scaling wall then the industry has no choice but to take replacements seriously.

That potential replacements like VG SOT MRAM can offer serious area advantages is no small incentive there too.

As long as they could provide adequate power the number of cores per socket could easily increase 50-70% at the same L2/L3 densities in the same space.

 

[adroc_thurston]

but if SRAM has run into a scaling wall then the industry has no choice but to take replacements seriously.

Ehhh gonna keep my hopium in "SRAM on CFETs scaling in like early 2030s" instead.

VG SOT MRAM can offer serious area advantages is no small incentive there too.

Yea but SOT-MRAM has so far been a meme, not a product, and I don't think it's anywhere close to being a product.
At least STT-MRAM is real and is slowly replacing eFlash.

As long as they could provide adequate power the number of cores per socket could easily increase 50-70% at the same L2/L3 densities in the same space.

Yea the ideal scenario but that's so unlikely to happen.

 

[soresu]

Yea but SOT-MRAM has so far been a meme, not a product, and I don't think it's anywhere close to being a product.

From what I can gather base SOT MRAM doesn't seem worth developing vs the VG SOT variant.

Imec demonstrated VG SOT MRAM in February (link) - they don't seem to do that just for the sake of it given their previous demonstrations of future transistor tech like forksheet.

As you say though it is at the least 5-10 years behind productisation as yet vs STT MRAM which is much more mature.

The advantage of cache stacking though is that AMD at least don't have to wait for a fully CMOS integrated node like STT MRAM has at some fabs.

Another thing being looked at by Imec is nanowire VFETs for SRAM (link), so there's that too I guess.

 

[adroc_thurston]

Imec demonstrated VG SOT MRAM in February (link) - they don't seem to do that just for the sake of it given their previous demonstrations of future transistor tech like forksheet.

Yea I've seen the paper, but given thet usual pattern of "imec talks, fabs do not" it's a fair while away from hitting relevant process nodes, unfortunately.

Another thing being looked at by Imec is nanowire VFETs for SRAM (link), so there's that too I guess.

Yea a by far more feasible choice, but either way that's years and years away and we need more SRAM now. Or yesterday, really.

 

[Markfw]

They're pretty good but I wonder if they're good enough.

Bingo.

Yea it was a rather solid design TLB bugs aside and in itself is a byproduct of like there dead K9 attempts.

Only one dumb youtuber did that.

RDNA3 still works as well as it should in headless compute.
Still a cursed piece of IP.

They're not projections, the Si has sampled and perf targets are now final.

I have posted links where Genoa set all sorts of world records, and they say its the fastest. I have posted my own benchmark results and said the same. But there seems to be no love on this forum for Genoa. I hope Zen 5 blows Zen 4 away, but I am more than happy with my 3 Genoa chips.

 

[adroc_thurston]

I hope Zen 5 blows Zen 4 away

It really does, but 500W socket power bites.

but I am more than happy with my 3 Genoa chips.

Genoa is still a very-very impressive offering, but per-core/per-thread perf of Turin is something else.

 

[Markfw]

It really does, but 500W socket power bites.

Genoa is still a very-very impressive offering, but per-core/per-thread perf of Turin is something else.

I have all my 7950x chips set to 142-150 watts (depending on BIOS) and my 3 Genoa chips are 320 watt. So I have 608 Zen 4 cores(threads) running at an average of ~4 ghz 100% full load for 1710 watts total. Just the 2 9554's are running a total of 256 threads@3.5 ghz for 640 watts ! 160 more threads @ 4.5 ghz full load. SR/Raptor lake can not touch the performance or the perf/watt. Even at 500 watts, it Zen 5 is that impressive (>20% IPC over Zen 4 + possible clock upgrade), then who cares about 500 watts for 96-128 cores (192=256 threads) for one chip !

 

[adroc_thurston]

Even at 500 watts, it Zen 5 is that impressive (>20% IPC over Zen 4 + possible clock upgrade), then who cares about 500 watts for 96-128 cores (192=256 threads) for one chip !

Eh, still tricky to cool, in 1U especially.

>20% IPC over Zen 4 + possible clock upgrade

It's all loaded in IPC, the clocks were effectively tapped out with Zen4 being a real speed daemon.

 

[Markfw]

Eh, still tricky to cool, in 1U especially.

It's all loaded in IPC, the clocks were effectively tapped out with Zen4 being a real speed daemon.

Now that could be, but I have seen several WC solutions that would work great, even at 500 watts, but the noise !!!!. Mine are on these:

Pardon Our Interruption...

The 1U and 2U solutions for WC are great, but noisey, and I don't want that, but in a real server floor ? Who cares about the noise.

 

[maddie]

Or bondrewd's misinterpretation of RDNA3.

Was trying to remember that name. His writing style has me experiencing some deja vu here lately.

 

[Triskain]

If you want something actually "substantial" out of him, you can go look at at his anime tiddie and deleted poasting twitter feed...

TDevilfish

Or just subtract 20-30% from everything he says, then you are in the right ballpark.

No ethnic slurs.
admin allisolm

 

[jpiniero]

If you want something actually "substantial" out of him, you can go look at at his anime tiddie and hohol poasting twitter feed...

TDevilfish

Or just subtract 20-30% from everything he says, then you are in the right ballpark.

Too bad that Enron made it so that you have to have an account to view Twitter.

 

[adroc_thurston]

Or just subtract 20-30% from everything he says, then you are in the right ballpark.

Lmao what

 

[yuri69]

20% seems like the floor to me given what AMD accomplished with Zen 3 and what Zen 5 is rumored to be.

Lol, what a deja vu from the Zen 4 rumors: "Zen 3 was 20% - now they got the funding, the 5nm doubles everything, the delay between releases gave them such opportunity!!1!"

Thinking like that brought us current Zen 4.

AMD is all about making economical stuff - they will still need to scale it to 4c APUs based on Zen 5. So those uber-wide cores don't really fit.

 

[adroc_thurston]

Lol, what a deja vu from the Zen 4 rumors: "Zen 3 was 20% - now they got the funding, the 5nm doubles everything, the delay between releases gave them such opportunity!!1!

Zen4 was always high single digits int, low teens total IPC bump.

AMD is all about making economical stuff

I wouldn't call MI300 economical on a good day.

they will still need to scale it to 4c APUs based on Zen 5

Wroooong because favela/mainstream mobile/edge/Telco segments are served by Compact piles.