- Mar 3, 2017
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Depends. last gen amd had an advantage because the processor was more sensitive to ram speeds. amd operating @ 3600 with fast ddr4 was blitzingly good. this gen neither are winning favours. there's a decent uplift from 5200 to 6000 and then it's very small after. as i posted recently you begin to see very good game performance at very high 7000 and beyond on intel. this is currently unrealistic due to the intel imc giving up in the low 7000's for most people. the zen 4 iod was already a relatively new design. amd's pain point is the speed being influenced by if limitaitons.I think base will be 6400 and OCers may get that upto 6800 or 7000. 7200 might be elusive for them. They have a bad track record with IMC having speed parity with Intel's that they couldn't shrug off with Zen 4. I mean, what are the chances that the I/O die will be a complete redesign instead of recycling/tweaking Zen 4's?
It'll be interesting to see if amd can repeat their past success by delivering a processor running at those clocks, say 6-6.1 ghz while intel will be pushing 6.5 to 6.8 or more in the coming generations, but matching or wiping the floor clean with intel's attempt. ignoring the decade of incompetence amd has always been better than intel at much lower clocks and temps. Except core. Core had both a freq regression that didn't affect its performance and a large noticeable turn back the clock on thermals. It was very impressive work by intel.I would hope so. For an overhaul of the core, it ought to be >15%.
Tbh, I think the bigger question that many aren't discussing is if Zen 5 supports much faster DDR5, ideally 7200 MT/s or higher. Memory latency has been a big weak point of Zen 4 and the AM5 platform, so it would be nice if AMD could ameliorate it in the next generation.
That's a huge jump. It's the same jump that occurred from Zen 2 -> Zen 3.
I personally don't care too much about clocks, but rather, overall perf/watt and absolute performance.It'll be interesting to see if amd can repeat their past success by delivering a processor running at those clocks, say 6-6.1 ghz while intel will be pushing 6.5 to 6.8 or more in the coming generations, but matching or wiping the floor clean with intel's attempt. ignoring the decade of incompetence amd has always been better than intel at much lower clocks and temps. Except core. Core had both a freq regression that didn't affect its performance and a large noticeable turn back the clock on thermals. It was very impressive work by intel.
when the holiday season approached stores set combo sales or reduced the price very little and the lines to got very long if you wanted to enter to get a chance to get one of them. I remember almost getting into fisticuffs with two separate men because they kept trying to cut people off.
these days you leave your mobile number with a ticket and they call you up if your number gets picked. sleeping inside your car in the parking lot with the heat on is a lot nicer than standing out in the snow or freezing rain. even have a snack in the card, like a butter and preserves sandwich and a banana on the side. with igor it'd be a few bunches of bananas as he read back love sonnets to them.
Clocks matter if an app likes the frequency better than the amount of data pushed by each clock cycle. there's not a lot of freq loving apps out there and this isn't a big deal for many, but it is for the few.I personally don't care too much about clocks, but rather, overall perf/watt and absolute performance.
It's not only about the improvements directly achieved but also the new technologies introduced (which can then be refined) and future improvements enabled by the changes (the usual even Zen gen).Why was Mike Clark so excited about it
Quantum wells, it's the answer to everything! 🤘how do you plan on cooling this monstrosity Tim?
I'm a bit confused here Doug. IPC is literally, Instructions Per Clock. I used to do calculations on this working on firmware development looking at how long a given instruction took to execute. We had to stick with C/C++ code for portability, but I had no problem tweaking the code to get the compiler to use slightly faster instructions.IPC has plenty to do with clockspeed. IPC will be higher than slower you clock, because DRAM is fewer cycles away. A design that targets a higher clock speed also has to increase cache latency (in terms of clock cycles) at every level; i.e. an L1 able to work at 1 cycle latency at clock x will require 2 cycles latency at clock 2x.
If they increase IPC by 19% it is very unlikely they will be able to maintain the same clock speed. I'm extremely skeptical of any claims that IPC can be increased by that much and clock rates can be increased as well. Sure, they are getting some "free" clock increase due to process, but there's less and less of that available with each process generation.
Even if Zen 5 is a clean sheet, Zen 4 is pretty good. There's no reason to believe we'll have a Zen 1 moment again if for no other reason than we're going to be comparing to something that isn't 15h.Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.
I think people are too locked into the weird geomean amd pushed with the Zen 4 preview last august. the performance leap should be interesting, but the price will be higher than what we've seen. economy should be better then hopefully but who knows.That's a huge jump. It's the same jump that occurred from Zen 2 -> Zen 3.
The words used to describe the new architecture for Zen 5 were the exact same words used to describe the new architecture for zen 3, in both cases AMD said "grounds up".Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.
I expect some interesting things from Zen 5 considering AMD is not developing cores on a shoestring budget anymore since a couple of years now.It's not only about the improvements directly achieved but also the new technologies introduced (which can then be refined) and future improvements enabled by the changes (the usual even Zen gen).
Also the excitement may be not only about the Zen cores but also the package layout with CCDs and one IOD that with Zen 4 was still essentially unchanged since Zen 2.
I'm a bit confused here Doug. IPC is literally, Instructions Per Clock. I used to do calculations on this working on firmware development looking at how long a given instruction took to execute. We had to stick with C/C++ code for portability, but I had no problem tweaking the code to get the compiler to use slightly faster instructions.
What we really have here, and this debate raged on ATF for a while, is Performance Per Clock - which is really an aggregate base on the execution of large instruction stream (from whatever benchmark being used). Ultimately, all I, and I would think most ppl care about is the actual performance delta between a Ryzen 6000 series and an 8000 series APU. +20% is pretty good gen-to-gen nowadays.
I recall this. I remember saying something like this on a now defunct blog but I was toasted in the comment replies. I had the same outlook when Ryzen launched; people presumed AMD were talking out of their ass when they claimed Ryzen would have a giant leap in performance over dozer. I don't remember the exact figure and whether it was overall performance or not. Sure enough they met that goal. Though that being in recent and thus fresh memory has led some of the wild claims about Zen 5 that have been circling like flies to a pile of horse crap. doesn't help when you have morons like mlid talking out of their behinds. Or the chunky boy with greasy curly hair. It's difficult to say what zen 5 would be like or what arrow lake would be like. I can take my best guess and post it here but my words as valid as the bs spewed by leakers.I remember when Apple announced A9 and claimed a 70% performance increase everyone thought that was crazy and they were cherry picking some corner case, then sure enough Geekbench showed a ~70% increase in ST thanks to the combination of IPC improvement along with a massive increase in clock rate. Now maybe they weren't using Geekbench specifically but it was interesting how that lined up so well with their claim in that instance. Obviously Apple was working from a much lower bar back then, everyone is subject to the law of diminishing returns after all.
how do you plan on cooling this monstrosity Tim?
i take back what i said earlier, iw ould love to see 2x 8+16 dies on ryzen. 16 big cores with smt and 32 small cores with cache and smt. cmon amd, make us happy and we'll shower you with our money.
Has anyone here postulated that Zen 5 being on N3 and N4 could mean that the single CCD SKUs may use N4 and the dual CCD ones may use N3? It's also possible that the E-core CCD may use N3 for minimal energy usage while the P-core CCD will benefit from the maturity of the N4 node family?
N4 for APUs and N3 for CCDs?If there is a node split I expect it is more likely to be APUs Vs CCDs.
N4 for APUs and N3 for CCDs?
N4P for everything except Breithorn-Dense.N4 for APUs and N3 for CCDs?
Golden Cove achieved a 19% IPC increase & clocked 0.2GHz higher than Cypress Cove.IPC has plenty to do with clockspeed. IPC will be higher than slower you clock, because DRAM is fewer cycles away. A design that targets a higher clock speed also has to increase cache latency (in terms of clock cycles) at every level; i.e. an L1 able to work at 1 cycle latency at clock x will require 2 cycles latency at clock 2x.
If they increase IPC by 19% it is very unlikely they will be able to maintain the same clock speed. I'm extremely skeptical of any claims that IPC can be increased by that much and clock rates can be increased as well. Sure, they are getting some "free" clock increase due to process, but there's less and less of that available with each process generation.
Frequency iso power. You might be able to hit higher peak ST max, but usually larger architectures take more power to reach the same frequencies as the previous architecture, which is way more of an important limiting factor in MT.Golden Cove achieved a 19% IPC increase & clocked 0.2GHz higher than Cypress Cove.
Zen 3 achieved a 19% IPC increase & clocked 0.2GHz higher than Zen 2.
What is the catch?
Instructions per clock can't be calculated by "looking at how long a given instruction takes to execute", at least not since the days of the 6502 (I remember doing what you are talking about programming an Atari 800's 6502 when I was in junior high) That sort of cycle counting is fine for something like 'MOV R2,0' (assuming you want to deal with figuring out how many instructions can issue and retire in a cycle, which gets more and more complicated the wider CPUs get) but you can't do it for everything.
You can always find the ideal CPI for any instruction just by counting the number of cycles it would take to execute. That may or may not be particularly useful, but I'm not aware of any instruction that takes a variable number of cycles to execute given a perfect cache.
Thankfully I left my assembler programming behind with the 6502 so I couldn't say if current CPUs like Intel/AMD's x86 or Apple/ARM AAarch64 have any instructions with variable timing but I wouldn't be surprised - I'd look at instructions doing stuff like multiplication and division first if I was trying to find such.