Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[naukkis]

Registers are basically virtual (remapped) until they enter the pipeline. Intel has 512bit ports that can for example

__m512i _mm512_permutex2var_epi32 (__m512i a, __m512i idx, __m512i b)
vpermi2d zmm, zmm, zmm

shuffle between lanes. This is what I call a flat register operation.

For operations within lanes it really matters not if its encoded as 2 avx or 1 avx512. The throughput is the same as is the order of operation. The only thing you're saving is the size of the instruction(s).

AMD Zen4 has also 512 bit ports. Only execution is 256 bit. As registers are full 512 bit shuffling between lanes isn't problem even with 256-bit execution units. Zen4 fpu is totally different to Zen1 which had 128 bit registers and ports and because of that if splitted 256 bit operations to 2x128bit instructions. Zen4 doesn't do that - 512 bit instructions goes through pipeline as one instruction.

If 512 bit instructions is split to 2 256-bit instructions and lane crossing instruction involves parts of both halves execution will many more instructions than just two and need additional register to register moves. Zen4 with 512 bit registers don't suffer any of those problems.

 

[Abwx]

About nothing that we didnt already knew on AMD latest com set apart that AM5 is confirmed to live at least till 2026 :

AMD Ryzen 8000: Präsentation nennt Zen 5 und „Navi 3.5“ auf AM5

AMD hat im Rahmen eines Partner-Webinars eine Roadmap gezeigt, die erstmals Ryzen 8000 mit Zen 5 und Navi 3.5 nennt.

www.computerbase.de

 

[Timmah!]

Maybe this is a defense of still doing 16c on Zen5 since those cores will no doubt be bigger.



I interpret this as possibly CPU's with both V-cache and E-cores (probably the rumored 'c' cores for AMD). I hope we won't have to deal with a scheduler that have to take 3 types of cores into account at the same time, like high cache, high clock, and high energy efficiency. Probably not though, as we're likely to not see more than 2 CCX'es, at least not in the consumer market.

I think for Zen5 I'd ideally still get the regular Zen5 with 16c to avoid the scheduler issues with V-cache (and iffyness with voltages we're currently seeing). If there's a version with b.L with Zen5c small cores, that might be tempting if there's user cases for more cores, since I have much more faith in the scheduling for b.L working properly after two generation of Intel CPU's with it. However, I've still yet to see a case with my current 7950X where I'd have preferred one Zen4c CCX with more cores for my current uses cases.

Pretty sure this points toward 8C + 16C (of "c" flavor) for Ryzen in the future. This allowing to retain only 2 dies that fit under the IHS. Probably happening with Zen "6" - or whatever it will be called. Since the "c" cores supposedly dont clock as high as the regular ones (right?), maybe they will drop the vcache in there (to make up for their smaller L3).
Cant say i am too happy about this. Still preferable option to rumored 8+32 solution from Intel (unless that will turn out somehow too good). Anyway, i hope it still happens on AM5 platform. Would like to upgrade my 7950x at some point to higher core count CPU without the need to get a new board.

 

[A///]

i think they'll maintain 16 large cores. amd isn't going the way like intel with their c cores. from what i understand they're shrunken down cores with smt and the same cache or slightly reduced cache. zen 6 may be on a new platform fwiw. we should know more about it within the next year as we get closer to the zen 5 release and amd loosens their death grip on their canaries.

 

[BorisTheBlade82]

Pretty sure this points toward 8C + 16C (of "c" flavor) for Ryzen in the future. This allowing to retain only 2 dies that fit under the IHS. Probably happening with Zen "6" - or whatever it will be called. Since the "c" cores supposedly dont clock as high as the regular ones (right?), maybe they will drop the vcache in there (to make up for their smaller L3).
Cant say i am too happy about this. Still preferable option to rumored 8+32 solution from Intel (unless that will turn out somehow too good). Anyway, i hope it still happens on AM5 platform. Would like to upgrade my 7950x at some point to higher core count CPU without the need to get a new board.

Expecting this as well - maybe even as a surprise for RYZEN 8000 already.

 

[A///]

I wonder if disenchantment knew anything when he made this topic because amd has traditionally skipped generational naming after zen 2.

 

[A///]

Expecting this as well - maybe even as a surprise for RYZEN 8000 already.

i take back what i said earlier, iw ould love to see 2x 8+16 dies on ryzen. 16 big cores with smt and 32 small cores with cache and smt. cmon amd, make us happy and we'll shower you with our money.

 

[Abwx]

Last rumours at NBC, from an usual suspect, some infos seems legit since they could have been guessed without much risks :

AMD Ryzen 8000 CPUs could bring up to Core i9-13900KS-level boost clocks, 25% more L1 cache, and double-digit IPC uplift vs Zen 4

After revealing the preliminary specifications of the Zen 5 architecture, Paul from RedGamingTech has given some more details regarding the new architecture. The leaker now alleges that AMD Zen 5 processors could have a larger L1 cache and a boost frequency of up to 6 GHz.

www.notebookcheck.net

 

[Timmah!]

i take back what i said earlier, iw ould love to see 2x 8+16 dies on ryzen. 16 big cores with smt and 32 small cores with cache and smt. cmon amd, make us happy and we'll shower you with our money.

8+16 per die and 2 such dies on Ryzen would be indeed more enticing, but i kinda doubt it. Going from 8 to 24 cores on a chip is rather massive increase, the c cores are not really smaller, right? Just have smaller cache.

 

[Timorous]

8+16 per die and 2 such dies on Ryzen would be indeed more enticing, but i kinda doubt it. Going from 8 to 24 cores on a chip is rather massive increase, the c cores are not really smaller, right? Just have smaller cache.

C cores on Zen4 are smaller.

 

[igor_kavinski]

An IPC of 19% over Zen 4 sounds kinda disappointing. I hope that's not true. Am I the only one who thinks that TSMC nodes have trouble hitting high frequencies?

 

[moinmoin]

the c cores are not really smaller, right? Just have smaller cache.

How in the world did the gush over in the Zen 4 thread miss you?

Page 501 - Discussion - Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

Page 501 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

The overall core area reduction was 35.4 percent.

 

[Saylick]

An IPC of 19% over Zen 4 sounds kinda disappointing. I hope that's not true. Am I the only one who thinks that TSMC nodes have trouble hitting high frequencies?

It sounds disappointing only because Zen 5 has been hyped up so much, but yeah, I too wish Zen 5 has more gains. You'd think with a major overhaul plus a widened front end that Zen 5 should have the largest IPC gain in the Zen family to date (not counting going from Bulldozer to Zen 1).

No, I don't think TSMC nodes have trouble hitting high frequencies. A few hundred extra MHz falls in line with what I'd expect for N5 to N4P.

 

[MrTeal]

An IPC of 19% over Zen 4 sounds kinda disappointing. I hope that's not true. Am I the only one who thinks that TSMC nodes have trouble hitting high frequencies?

+19% ST at the same clocks? That sounds like a pretty good generational gain to me.

 

[biostud]

An IPC of 19% over Zen 4 sounds kinda disappointing. I hope that's not true. Am I the only one who thinks that TSMC nodes have trouble hitting high frequencies?

IPC has nothing to do with the clock speed, but overall if anyone think that generational performance increase (IPC*clockspeed increase) is more than 20-30%, then prepare to be disappointed.

 

[Doug S]

IPC has nothing to do with the clock speed

IPC has plenty to do with clockspeed. IPC will be higher than slower you clock, because DRAM is fewer cycles away. A design that targets a higher clock speed also has to increase cache latency (in terms of clock cycles) at every level; i.e. an L1 able to work at 1 cycle latency at clock x will require 2 cycles latency at clock 2x.

If they increase IPC by 19% it is very unlikely they will be able to maintain the same clock speed. I'm extremely skeptical of any claims that IPC can be increased by that much and clock rates can be increased as well. Sure, they are getting some "free" clock increase due to process, but there's less and less of that available with each process generation.

 

[H433x0n]

An IPC of 19% over Zen 4 sounds kinda disappointing. I hope that's not true. Am I the only one who thinks that TSMC nodes have trouble hitting high frequencies?

That's a huge jump. It's the same jump that occurred from Zen 2 -> Zen 3.

 

[igor_kavinski]

Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.

 

[biostud]

Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.

19% IPC + 10% clock ~30% increase, which is pretty good for a generational leap.

 

[igor_kavinski]

19% IPC + 10% clock ~30% increase, which is pretty good for a generational leap.

If that's true, I guess I can live with that

But that's ST, right?

MT would be what? 30-40% increase minimum?

 

[Saylick]

19% IPC + 10% clock ~30% increase, which is pretty good for a generational leap.

I don't think we're going to get +10% clocks, more like 4% (going from 5.7 GHz to 5.9 GHz max ST boost).

Unless the IPC gains are in the low 20s, Zen 4 might bring more of a ST uplift than Zen 5.

 

[Abwx]

I don't think we're going to get +10% clocks, more like 4% (going from 5.7 GHz to 5.9 GHz max ST boost).

Unless the IPC gains are in the low 20s, Zen 4 might bring more of a ST uplift than Zen 5.

AMD s Mike Clarck more or less hinted that it would be a bigger improvement than Zen 4 13% IPC uplift over Zen 3, frequency wise that should be within 3-4% uplift over Zen 4 wich can clock up to 5.8 in some instances.

 

[A///]

8+16 per die and 2 such dies on Ryzen would be indeed more enticing, but i kinda doubt it. Going from 8 to 24 cores on a chip is rather massive increase, the c cores are not really smaller, right? Just have smaller cache.

how do you plan on cooling this monstrosity Tim?

 

[Saylick]

AMD s Mike Clarck more or less hinted that it would be a bigger improvement than Zen 4 13% IPC uplift over Zen 3, frequency wise that should be within 3-4% uplift over Zen 4 wich can clock up to 5.8 in some instances.

I would hope so. For an overhaul of the core, it ought to be >15%.

Tbh, I think the bigger question that many aren't discussing is if Zen 5 supports much faster DDR5, ideally 7200 MT/s or higher. Memory latency has been a big weak point of Zen 4 and the AM5 platform, so it would be nice if AMD could ameliorate it in the next generation.

 

[igor_kavinski]

Tbh, I think the bigger question that many aren't discussing is if Zen 5 supports much faster DDR5, ideally 7200 MT/s or higher. Memory latency has been a big weak point of Zen 4 and the AM5 platform, so it would be nice if AMD could ameliorate it in the next generation.

I think base will be 6400 and OCers may get that upto 6800 or 7000. 7200 might be elusive for them. They have a bad track record with IMC having speed parity with Intel's that they couldn't shrug off with Zen 4. I mean, what are the chances that the I/O die will be a complete redesign instead of recycling/tweaking Zen 4's?