Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[PJVol]

They already have built in regulators per core since Zen 1, what Intel will implement as DLVR.

I wasn't asking about regulators per se

 

[Abwx]

I wasn't asking about regulators per se

Then you re asking about something whose significance is unknown for you..

Have you heard of any plans to design FIVR-based PDN for Zen6?

Do you know what is FIVR..?..

Fully Integrated Voltage Regulator.

 

[PJVol]

Then you re asking about something whose significance is unknown for you..

Once more, I wasn't asking about specific regulator, but about the likely design and implementation of PDN in general, or was I unclear?

Do you know what is FIVR..?..

Fully Integrated Voltage Regulator.

Oh... I appreciate your knowledge but please don't bother yourself anymore (lest you be embarassed)

 

[soresu]

N5 was the last major one for speed until like the CFET era.

So not even Forksheet nodes?

 

[adroc_thurston]

So not even Forksheet nodes?

Those are just to keep the semblance of power/perf scaling going, just like nanosheet GAAs.

 

[Abwx]

Have you heard of any plans to design FIVR-based PDN for Zen6?

Once more, I wasn't asking about specific regulator, but about the possible design and implementation of PDN in general, or was I unclear?

Oh... I appreciate your knowledge but please don't bother yourself anymore.

The one bothering himself is the one who use an acronym without even knowing what it means, and what are the currently used technologies,.

Zen has by the definition a PDN since the voltage regulation, or if you prefer the power delivery, is done on a per core basis, i mentioned it but one should read more accurately..

To make you better understand each core has its dedicated voltage regulator, akin to linear regulators since these are switched mode but without inductance like in Haswell where it was done at the whole CPU level using inductances, but that s not efficient, hence Intel ditching the concept.

 

[PJVol]

OMG ... please stop ))
I didn't ask you about any clarifications, so please, keep your lectures on PDN basics for the reddit.

 

[Abwx]

So the point was to troll the thread..?..

 

[A///]

Oh... I appreciate your knowledge but please don't bother yourself anymore (lest you be embarassed)

rivatuner guy? your response reads like him

 

[PJVol]

rivatuner guy? your response reads like him

This comparison should flatter me up? )
(no idea who the **** he is)

 

[A///]

I my talking of real TDP, not of the fake TDP advertised by Intel, the 13900K is advertised as 125W but we all know that it stick to 250W when loaded by whatever multithreaded load.

only if you lock it to 250w in the bios. otherwise it will go higher and higher. intel all alone could advertise their cpus as eco friendly heating units in comparison with burning natural gas for heat in winter.

 

[DisEnchantment]

They already have built in regulators per core since Zen 1, what Intel will implement as DLVR.

Zen 1 has LDO not IVR. Purpose is same, just different characteristics

 

[Abwx]

Zen 1 has LDO not IVR. Purpose is same, just different characteristics

i explained the thing, Intel s Haswell IVR was setting the voltage for the full CPU, that is, a single rail regulator while AMD solution implement a per core regulator, whatever the name.

Haswell IVR use inductances, this guarantee a high efficency for the regulator itself, but since it feed all the cores with a single voltage the end result is inefficient, not counting that you can hardly implement big inductances on the silicon, so these were external.

AMD s LDO use a switching mode supply for each core, basically that s a high speed switch made of parralled mosfets that charge a capacitor untill the voltage reach the targeted value, at wich point it is stabilised by fixing the switch duty rate at the convenient value.

Since it doesnt use inductances this amount to a linear regulator efficency wise, so not very good intrinsically but this is largely compensated by the per core separate regulators, i once made here a basic math demonstration of the advantage in reducing power at average loadings with such a scheme.

 

[Anhiel]

I my talking of real TDP, not of the fake TDP advertised by Intel, the 13900K is advertised as 125W but we all know that it stick to 250W when loaded by whatever multithreaded load.




You stated a 51000 Cinebench score for ARL that is roughly 35% higher than the 13900K, Igors lab say that it s someething like 10-15% in MT, so you stated 2.3-3.5x the leaked improvement.

Since you said 48000 for Zen 5 it s obvious that you are feeding yourself with hopes that it well perform lower than ARL 8 + 16, unfortunately for you that wont be the case.




Possibly that they added a 2 x 256b unit, otherwise what would be the use to increase L1 size by 25%..?

This would allow to execute either a second 512b instruction, or 2 x 256b/128b/64b instructions, not economical to use a 256b unit to process a 64b instruction, but since it s there it s better than to add a separate 64b unit.

I calculate for TDP not something else so why pulling something that has a complete different definition to begin with?
Besides that's what Intel is selling and tiering the SKU's. So why would I have to go with something that is lottery random instead of matching what they will be selling it for?

I did say "in theory" and I also did say it was based on leakers (MLID) so blame them for the inaccuracy.
Besides this was before Intel started axing designs and pulling follow-on designs up ahead of schedule as replacement and before Intel ditched the very design I theorized there for one without hyperthreading.

Eh? What do calculations have to do with hopes? It's the calculation that tell the situation in the first place, hence, my conclusion based on that. You got things backward here.
That said Intel's axing actions already proofed those original designs weren't up to the task to beat Zen5. Silently replacing the engine and claiming it was originally better? Is that it now?

 

[Abwx]

I calculate for TDP not something else so why pulling something that has a complete different definition to begin with?
Besides that's what Intel is selling and tiering the SKU's. So why would I have to go with something that is lottery random instead of matching what they will be selling it for?

They are selling it as an actual 250W CPU with a 125W moniker, i woud think that in a technical forum it s the real values that are of concern, not imaginary numbers forged to dupe the consumers.

I did say "in theory" and I also did say it was based on leakers (MLID) so blame them for the inaccuracy.
Besides this was before Intel started axing designs and pulling follow-on designs up ahead of schedule as replacement and before Intel ditched the very design I theorized there for one without hyperthreading.

Eh? What do calculations have to do with hopes? It's the calculation that tell the situation in the first place, hence, my conclusion based on that. You got things backward here.
That said Intel's axing actions already proofed those original designs weren't up to the task to beat Zen5. Silently replacing the engine and claiming it was originally better? Is that it now?

I guess that MLID had noises of previous targeted perfs and that he took them at face value thinking that it was real silicon, Igor s Lab got something a little better accuracy wise apparently.

Surely that Intel prefered a much shorter time to market than a very late one, even if that means being in the rear view mirror for yet another cycle if we are to half believe the latest Zen 5 rumours from RGT.

 

[DisEnchantment]

AMD s LDO use a switching mode supply

Linear regulation not switching. Not sure about your source of AMD's LDO being switching regulators.

Also Stilt has described them here https://forums.anandtech.com/threads/ryzen-strictly-technical.2500572/

Zeppelin is the first design in which AMD has extensively utilized integrated voltage regulators. Unlike the fully integrated voltage regulator (FIVR) used in Haswell and Broadwell CPUs, AMD's regulator implementation isn't based on ultra-high speed switching circuitry. The integrated voltage regulators in Zeppelin are ultra-high efficiency digital low-dropout (dLDO) type of regulators. Most of the different domains (cores, caches, data fabric, etc.) have their own dLDOs and they can all be controlled individually.

 

[Abwx]

View attachment 84229
Linear regulation not switching. Not sure about your source of AMD's LDO being switching regulators.

Also Stilt has described them here https://forums.anandtech.com/threads/ryzen-strictly-technical.2500572/

I know this, i said this is akin to a linear regulation when it comes to the way it works electrically speaking and for efficiency, that is, high speed switching to charge a capacitor.

When a capacitor is charged through a high speed switch the switch conduction time is the equivalent of a resistance, the lower the on switching time the higher the resistance and hence the voltage at the capacitor ends and inversely, the power dissipated by the switching mosfets is the same as the one dissipated by the equivalent resistance.

A real switching mode supply use an inductance that is charged by the switching mosfet during a cycle, the next cycle the energy stored in the inductance is used to charge a capacitor, in this case the loss in the mosfet is negligible.

This way there s very little loss and most of the energy is stored in the inductance, there s a little loss because the inductance will output an AC current that need to be rectified using mosfets as diodes but this is marginal and efficency can be above 90% while a linear regulator cant go significantly above 50%, in a LDO the saving is elswhere because of the core being a dynamic load that has not fixed voltage vs frequency and each core not forcibly working at the same frequency.

Edit : To end the debate you have the explanations at the begenning of this article, the two first chapters are enough to understand how AMD s LDO work :

Switched capacitor - Wikipedia

en.wikipedia.org

 

[TESKATLIPOKA]

Videocardz.com
Some Strix Point data. A lot of It looks inaccurate.

@Abwx That's why I wrote a lot of the data looks incorrect.

 

[Abwx]

Videocardz.com
Some Strix Point data. A lot of It looks inaccurate.

The L2 caches sizes are dubbious, it display 1MB/core for 4 cores and then 2x1MB for all 8 remaining cores, and a pic say 8MB L3 and the other 16MB.

Also clocks are completely erroneous.

 

[PJVol]

Linear regulation not switching. Not sure about your source of AMD's LDO being switching regulators.

Lol ... somehow he managed to throw three different types of VR together and put it in one Zen package

"...AMD s 1) LDO use a 2) switching mode supply for each core..."
...
...
"...the two first chapters are enough to understand how AMD s LDO work:

3) Switched Capacitor wikipedia

 

[PJVol]

Edit : To end the debate you have the explanations at the begenning of this article, the two first chapters are enough to understand how AMD s LDO work

Sorry, but I have to admit, you are completely lost in the dark a little bit lost ))
That article has little to do with Zen's PDN implementation. And if you really want to understand what's under the hood, wiki is not a good source.
Here is a couple of AMD docs with a detailed explanation of the subject where one being continuation of another, first is more on physical layout of supply adjusting block (pmos headers), 2nd describes the controller logic:

US10218273B2 - On die voltage regulation with distributed switches - Google Patents

A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve...

patents.google.com

US9946278B2 - Droop detection for low-dropout regulator - Google Patents

A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (DLDO) control system comprising first and second regulators that generate a plurality of control signals to regulate an...

patents.google.com

 

[Joe NYC]

Videocardz.com
Some Strix Point data. A lot of It looks inaccurate.

@Abwx That's why I wrote a lot of the data looks incorrect.

It looks encouraging that samples of these are out already.

Compared to Zen 4, desktop Zen 4 launch was ~Sep 2022, Phoenix announcement in Jan 2023, while shipping products only started appearing in volume in ~ June 2023.

It looks like AMD may compress this time with Zen 5 generation.

 

[adroc_thurston]

It looks encouraging that samples of these are out already.

Yea, server ones have been out for a while.

It looks like AMD may compress this time with Zen 5 generation.

Yea went better than expected and stuff got pulled in.

 

[igor_kavinski]

Yea went better than expected and stuff got pulled in.

We gonna have Zen5X3D on shelves in March 2024?

 

[gdansk]

We gonna have Zen5X3D on shelves in March 2024?

No. Desktop doesn't matter. Shelves don't matter.