Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[biostud]

AMD said there was issues and he doesn't believe AMD so obviously theres no issues and the delay is because AMD felt like it.

Maybe they really are waiting for the 14900K fix so they truly can obliterate them in launch benchmarks.

 

[therealmongo]

Lol, who left the children have access to their devices 😂

 

[igor_kavinski]

AMD said there was issues and he doesn't believe AMD so obviously theres no issues and the delay is because AMD felt like it.

There probably IS an issue but not the one that AMD is telling us.

 

[igor_kavinski]

Maybe they really are waiting for the 14900K fix so they truly can obliterate them in launch benchmarks.

YES.

BINGO!

Now that's a logically possible motive behind AMD's decision. The greater the average performance percentage difference, the better Zen 5 looks to the public!

AMD should've just said so.

"We regret to inform you that we don't feel this is the right time to publish Zen 5 benchmarks. We will wait for our dear competitor to get their act together before we thoroughly embarrass them".

 

[StefanR5R]

Ian said that Zen 5c would see a much smaller drop in frequencies compared to what Z4c had relative to the classic cores.
Interesting.

Well, this expected if they talk about Epyc : 4nm vs 3 nm

No. AMD said this during the post-tech-day briefing in the context of Strix Point's N4P Zen 5 cores and N4P Zen 5c core sizes, the latter being just 25% smaller than the former. (Whereas the difference was 35% between Phoenix 2's Zen 4 and Zen 4c cores.) These lowered space savings are because AMD had to work within stricter constraints WRT Voltages and clocks in order to make the compact cores work as a support to the classic cores the way as AMD wanted them.
(Source: Computerbase's article on this briefing. Also take Tom's Hardware's interview with Mike Clark in which the Zen 5c design targets are discussed in the context of heterogeneous CPUs, read: Strix Point. PS, I haven't watched the Cutress X Cozma video.)

 

[StefanR5R]

BINGO!

Now that's a logically possible motive behind AMD's decision.

Okay... AMD are lying publicly when they say that they had a QA issue with the first batch. From this follows that they are either going on lying publicly by saying that they are recalling the first batch from their channel partners, or it follows that they are happy to sink the cost of the product recall just for the nicer comparison in reviews.

Further, according to you guys, AMD either has the power to make Intel publish their microcode update several days before August 8 when single-CCD Ryzen 9000 go on sale and the corresponding review embargo ends. Or AMD had told another lie and they will delay and delay the sales start and embargo for as long as Intel hasn't published the finalized microcode.

All very logical.

 

[Goop_reformed]

YES.

BINGO!

Now that's a logically possible motive behind AMD's decision. The greater the average performance percentage difference, the better Zen 5 looks to the public!

AMD should've just said so.

"We regret to inform you that we don't feel this is the right time to publish Zen 5 benchmarks. We will wait for our dear competitor to get their act together before we thoroughly embarrass them".

Nah. If that is the case they wouldn't have to reexamine the entire current inventory.

 

[igor_kavinski]

Nah. If that is the case they wouldn't have to reexamine the entire current inventory.

OK, you are telling me that they will get the CPUs back, every single one of them, run them through their QA test gauntlet and get them back on shelves ON August 8th for the single CCD CPUs????

Please, please THINK about that for a second.

Doing that FOR all shipped CPUs regardless of region or territory means they have testing facilities in every region within reach. Please tell me that you don't believe that to be true because that would be ABSURD. Even Intel doesn't have that.

 

[StefanR5R]

If that is the case they wouldn't have to reexamine the entire current inventory.

...only a part of the inventory which was first to arrive at distributors.
(Besides, they might just discard it rather than refurbish it.)

--------

So AMD have a new microarchitecture, and the first products with it which make it to the market are laptop computers, not mere desktop chips this time around. I don't recall that there is precedence.

And we're going to deliver 3nm here in short order with 4nm; basically, they're on top of each other.

Does this mean that Turin-dense is going to be early, or that Turin-classic is going to be late?

 

[igor_kavinski]

(Besides, they might just discard it rather than refurbish it.)

If it comes to that, they will sell it in bulk to Chinese businesses and then you bet you will find them on Ali Express.

 

[yottabit]

Yeah, by a lot, each CCD gets 2*32B fabric uplink (aka the new norm going forward).

That's not the limiting factor at all.

LPDDR5x @ 8533 MHz with 256-bit interface is 273 GB/s.

And I believe DDR5 @ 8000 MHz dual channel would be ~ 128 GB/s ? So over twice the membw

I don't understand the significance of the 2*32B fabric uplink thing if anyone cares to expand on that. I can't imagine that would bottleneck DRAM bandwidth right? But I'm guessing improves inter-CCD communication?

 

[Det0x]

~70 GB/s read is the hardlimit @ 2200mhz FCLK for a single set of GMI links (single CCD), even at 8800MT/s memory speed)


~76.5k GB/s read is the hardlimit @ 2400mhz FCLK


And ~81 GB/s read is the hardlimit @ 2550mhz FCLK


You only need ~6000MT/s memory speed to fully saturate 2500mhz FCLK read limit (screenshot below is not mine)


Like i wrote on previous page, Zen4 and now Zen5 is pretty much all read bandwidth limited by FCLK, while write is not.
You gain like + ~50% read bandwidth compared to single CCD when running a dual CCD CPU.

So theoretical, if the italian guy were really running 2400mhz FCLK on the 9900X, he would have around ~115GB/s read numbers in Aida

 

[CouncilorIrissa]

And I believe DDR5 @ 8000 MHz dual channel would be ~ 128 GB/s ? So over twice the membw

I don't understand the significance of the 2*32B fabric uplink thing if anyone cares to expand on that. I can't imagine that would bottleneck DRAM bandwidth right? But I'm guessing improves inter-CCD communication?

AMD’s Zen 4, Part 3: System Level Stuff, and iGPU

We covered Zen 4’s core architecture in depth in two articles.

chipsandcheese.com

A Zen 4 CCD has a single 32B/cycle fabric uplink, which means that single-CCD part can't have read bandwidth of higher than 64 GB/s (at FCLK of 2000 MHz that is).

 

[APU_Fusion]

The hysteria is being overclocked to the max here with voltage set to red.

 

[igor_kavinski]

The hysteria is being overclocked to the max here with voltage set to red.

Still below Intel's CPU killing voltage.

 

[BigIronOnHis]

OK, you are telling me that they will get the CPUs back, every single one of them, run them through their QA test gauntlet and get them back on shelves ON August 8th for the single CCD CPUs????

Please, please THINK about that for a second.

Doing that FOR all shipped CPUs regardless of region or territory means they have testing facilities in every region within reach. Please tell me that you don't believe that to be true because that would be ABSURD. Even Intel doesn't have that.

The CPUs sold in a few weeks will not be the same ones that are being recalled lol. The delay is likely just the time needed to ship out and restock shelves with chips that have been fully validated.

 

[igor_kavinski]

The delay is likely just the time needed to ship out and restock shelves with chips that have been fully validated.

Possible I guess. Still, it would have been better if AMD had disclosed the exact nature of the issue and how an improperly validated CPU was gonna behave because quite a few people out there may have paid full or even more than full price for their CPUs that weren't supposed to be on sale yet and they will live with them and encounter some weird issue and think AMD sucks and the retailer isn't gonna bother about calling the customer to get that CPU back because they already got what they wanted: the customer's cold hard cash!

 

[IEC]

Read your statement. Then read it again.

If it's due to not having run all the validation checks as the statement by AMD's spokesperson says, AMD wouldn't know with reasonable certainty (99.999%+) how the CPU would behave - and that's the point of recalling it!

Possible I guess. Still, it would have been better if AMD had disclosed the exact nature of the issue and how an improperly validated CPU was gonna behave because quite a few people out there may have paid full or even more than full price for their CPUs that weren't supposed to be on sale yet and they will live with them and encounter some weird issue and think AMD sucks and the retailer isn't gonna bother about calling the customer to get that CPU back because they already got what they wanted: the customer's cold hard cash!

 

[igor_kavinski]

If it's due to not having run all the validation checks as the statement by AMD's spokesperson says, AMD wouldn't know with reasonable certainty (99.999%+) how the CPU would behave - and that's the point of recalling it!

I hear you.

I just can't wrap my head around the timing of this recall and how the heck so many chips evaded a full validation check. Either AMD should have told us nothing or they should tell us clearly what the heck happened and under what circumstances.

 

[branch_suggestion]

N3E is enterprise/server, N3 is efficient junk. N3P is the value play performance/efficiency mainstream 3nm. N3X is for Nvidia, high end performance and increased silicon density.

First N3E part in GA is M4, that is the opposite of a server part.
N3B has parts across the spectrum and is expensive.
N3P will have parts across the spectrum, it will fully replace N3E eventually.
X nodes are niche. Nothing is stopping any of the big companies from paying for the best possible node available, the really expensive stuff is HBM and the really advanced packaging.

 

[branch_suggestion]

Is AMD paying you for your statement? Or are you an AMD voluntary public service agent here on the forum?

Ah, so you are green with envy after all.
Last statement, Nodes are nodes, nobody gets special treatment from TSMC.

 

[RnR_au]

Not sure if this tidbit has been mentioned yet (thread moves faaast...)

More tentative pricing... from China... and seems to match the Best Buy leak from earlier...

According to the retailer, the AMD Ryzen 9 9950X 16-Core CPU would cost $499 US (3631 RMB), the Ryzen 9 9900X 12-Core CPU would cost $399 US (2904 RMB), the Ryzen 7 9700X 8-Core would cost $299 US (2176 RMB) while the Ryzen 5 9600X 6-Core CPU would cost $229 US (1666 RMB).

https://wccftech.com/chinese-shopke...5-desktop-cpu-prices-lower-ryzen-7000-series/

Although it could be that the Chinese store owner is a reader of Anandtech forums...

 

[adroc_thurston]

N3E is enterprise/server

No.

N3 is efficient junk

No, N3b is an entirely different node altogether.

N3P is the value play performance/efficiency mainstream

No.

N3X is for Nvidia

That's an overdrive node strictly for AMD usage more or less.

 

[poke01]

is the zen 5 X3D still launching in September?

I kinda doubt it now. Probably CES 2025.

 

[Hail The Brain Slug]

is the zen 5 X3D still launching in September?

I kinda doubt it now. Probably CES 2025.

If they can release it to compete head-to-head against Intel's next gen for the gaming crown, I don't know why they would artificially delay to CES and potentially give Intel a few months of the gaming crown (pending how the new processors actually perform, of course).