Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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MS_AT

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Jul 15, 2024
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The L1/L2 BTB is indeed curious, as for the FP pipe methink that it s related to the 3/1 L/S ratio that limit the effective pipes utilisation to 3 ops/cycle, if the operands cant be loaded more pipes will have no effect for the thoughput.
They could mark that on the slide, like 3 (effective) with explanation at the end of the slide deck. I might be nitpicking but I think the quality of AMD press materials is getting worse instead of getting better. Actually that was 1 FP512 load per cycle and 0.5 store per cycle. But still the execution pipes won't go to waste if you do something more than shuffle memory around and keep data in the registers.
 

mostwanted002

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gdansk

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It's really joever for intel.. is it??
I really don't want to talk about Intel products in this thread.

In any case I say both x86-64 vendors have been caught slacking with desktop.
 
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inf64

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Mar 11, 2011
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Last minute delay incoming? Wouldn't look too bad considering intel are cooking themselves, literally.
The CPUs are on sale, I doubt there will be any delays. Supply might be an issue though, supposedly very little 9950x samples were sent to reviewers.
 

exquisitechar

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Apr 18, 2017
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It's really joever for intel.. is it??
Really want to see the efficiency of both, but Granite as well as ARL-S seem to be a disappointment in terms of performance. Don’t care who wins by a tiny margin. Well, the silver lining for AMD is that they’re on N4P instead of N3, at least…
 
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Hail The Brain Slug

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gdansk

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Charlie's got an article:

Charlie said:
history says wait for the half step when the power functions are debugged
I think that's good advice.

But it is funny how much AMD bends over backward to accommodate Microsoft (Pluton, bigger NPU) and keep getting shafted for it (not used in any current Surface products, missing CoPilot PC features despite being adequate).
 

mpumalanga

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Feb 18, 2022
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Charlie's got an article:


No real new information in that article.
Charlie just copied AMD's slides and is complaining and whining excessively, which is of course his style of writing and sometimes quite nice to read.

Nevertheless he should have been reporting and commenting on the new features of zen 5. Regardless how bad AMD's tech day supposedly was.

Otherwise why write an article in the first place ?
 

jdubs03

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Oct 1, 2013
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In CB r23, that QS at 253W gets beaten by 9950X ES between 160 to 200W.

Pat better get to church fast and pray for a miracle.
It’s a tough comparison. If we’re considering a water-cooled 9950x with PBO+CO, vs Intel 285K stock; it isn’t that much of a surprise to beat it.

Let’s see like for like, and then the scores will speak for themselves. I think it’ll be very close for pure performance.

Edit: If it’s not even, or Intel slightly ahead then they would’ve lost the MT advantage they had (with the caveat of instability/degradation, no small thing). Looks like ST is neck and neck as well. Now if Intel is a lot better on efficiency due to those E cores, maybe it won’t look so bad.
 
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Hitman928

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Apr 15, 2012
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It’s a tough comparison. If we’re considering a water-cooled 9950x with PBO+CO, vs Intel 285K stock; it isn’t that much of a surprise to beat it.

Let’s see like for like, and then the scores will speak for themselves. I think it’ll be very close for pure performance.

AMD says that the 9950x scores ~42k in Cinebench r23 MT at stock. That's the number I would go with, though the power consumption isn't known. It can use up to 230W, but there's reason to believe it doesn't actually use quite that much.
 

Saylick

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Sep 10, 2012
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What do you mean with regression? It's not slower, right? Or do you think about performance per area or something?
They mean that Lion Cove (LNC) is advertised as being +14% IPC over Redwood Cove (RWC), which is used in Meteor Lake (MTL). However, RWC is slower than Raptor Cove (RPC), which is used in Raptor Lake. Desktop Arrow Lake (ARL-S) uses LNC P-cores and is the successor to Raptor Lake. Therefore, the expected IPC uplift from Raptor Lake's P-cores to Arrow Lake's P-cores is likely less than 14% IPC uplift.
 

Josh128

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Oct 14, 2022
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So back to Zen 5. Apparently 90C on Zen 5 does not equal 90C on Zen 4 due to different thermocouple/RTD placement.

We also know Zen 4 hits 220W-230W stock on good cooling in full MT workloads but Zen 5 seems to top out at ~190ish in its stock mode, despite displaying cooler core temps than Zen 4. Its a strange thing-- I'd be very curious if 200W PPT Zen 4 = 200W PPT Zen 5 if you actually measured power draw from the wall. They use the same mobos, so it would be a valid comparison. Just seems weird that they wouldnt choose to make Zen 5 hit max PPT out of the box to get that sweet ~44-45K number.
 
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Joe NYC

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Newsflash: it isn't.
LNC is 14% off the RWC which is a real, real bad baseline (itsa regression off RPC despite the L2 bump).

The memory latency from on-chip memory controllers to crossing from chiplet to chiplet seems to be contributing (negatively), the same as with MTL.

Intel has a quite a bit of total cache to compensate for it. 76 MB L2+L3. That's between 40 MB for plain 9700 and 104 MB for x3d

 

Saylick

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Sep 10, 2012
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So back to Zen 5. Apparently 90C on Zen 5 does not equal 90C on Zen 4 due to different thermocouple/RTD placement.
Yeah, according to Zen Daddy Mike Clark, they put the temperature sensor closer to the hotspots so it's more accurate in Zen 5. In Zen 4, the temp sensor has a larger built-in margin to account for the lower accuracy in its placement, meaning the sensor would artificially report a higher temp because it wasn't exactly in the ideal spot (for safety reasons). If the placement is more ideal, that artificial buffer can be reduced and in theory the chip can push itself harder.
 

Doug S

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No real new information in that article.
Charlie just copied AMD's slides and is complaining and whining excessively, which is of course his style of writing and sometimes quite nice to read.

Nevertheless he should have been reporting and commenting on the new features of zen 5. Regardless how bad AMD's tech day supposedly was.

Otherwise why write an article in the first place ?

Why should he report on the new features of Zen 5? You can get that everywhere on the internet, that's not what people come to Charlie's site for. What you want is for them to release that information, give people like him time to digest it and come up with a list of questions, then provide enough Q&A time for him and other members of the press to ask and have answered their questions about the information.

It sounds like they barely allotted any time for Q&A, and to the extent they did they turned every question into something they could answer with "AI". Obviously they were told to do so by some marketing idiot up on high.

That's the kind of thing you read him for - to understand what is happening behind the scenes at a company. So why does AMD appear unwilling to talk about Zen 5 other than in context of "AI AI AI"?

Pointing out the Pluton thing is good too, as AMD apparently LEFT IT OUT OF THE BLOCK DIAGRAM until Charlie (and perhaps others, to be fair) called them out on it. Why do they want to hide that? Could it be because they know while it is something Microsoft wants, it is not something any of their customers want?