Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

Not Zen 3 levels of improvement

Zen3 wasn't doing the bulkiest, most overkill AVX-512 implementation known to man.
The bulk of area growth for Z5 is it.

 

[luro]

Apparently I woke up on the darkest timeline side of the bed today since I've learned that MLID was apparently correct.

Tech bros, I'm not feeling so well right now.

lmfaooo

 

[Joe NYC]

Lol, getting within 1mm2 is probably purely luck on my part since it depended on which pixel I measured from.

Fwiw, TSMC N4P comes with a 6% reduction in area for logic in comparison to TSMC N5, but 16% higher IPC with a 26% larger core and presumably 34% more transistors (1.25*1.06 = 1.34) is right on the money with respect to the square law of scaling (square roof of 1.34 = 1.15). Not Zen 3 levels of improvement (19% higher IPC, 200 MHz higher max clocks, for 8% larger CCD) but at least Zen 5 isn't under par. I'm hoping that the 16% IPC uplift is true for general performance and not significantly skewed due to AVX512.

I have a feeling 16% IPC gain underrepresents AVX-512 gains.

We will see what the future holds, but AVX-512 may end up under-utilized. Without NPU (being force fed on the industry), the same workloads running on CPU would have received performance uplift. Now those types of workloads may end up being diverted to NPU resulting in less utilization o AVX-512

 

[Joe NYC]

Zen3 wasn't doing the bulkiest, most overkill AVX-512 implementation known to man.
The bulk of area growth for Z5 is it.

We will see how good this bet by AMD on AVX-512 will turn out in the long run. AMD had a good enough implementation in Zen 4 and they doubled down on it.

 

[gdansk]

We will see how good this bet by AMD on AVX-512 will turn out in the long run. AMD had a good enough implementation in Zen 4 and they doubled down on it.

Not sure how useful it is for consumers outside of PS3 emulation but for the HPC market? Could be good.

 

[adroc_thurston]

Not sure how useful it is for consumers outside of PS3 emulation but for the HPC market? Could be good.

Not very, Intel doesn't support the ISA in client.

 

[jpiniero]

We will see how good this bet by AMD on AVX-512 will turn out in the long run. AMD had a good enough implementation in Zen 4 and they doubled down on it.

AI obviously.

 

[Anhiel]

Well, a singular vector unit is still a much better racing engine than NPU and the like albeit not as massive parallel. Future matrix engine with the latest matrix math will be better but that's at least 6 years away. There are some "regular" application that use it so it's always good to have it on hand.
The problem is more about Intel abandoning it for the new modified AI/matrix leaning AVX-10. So software adoption is gonna be worse than not.
AVX-10 is more future proof for upcoming massive parallel designs. So the change is not entirely aimed against AMD albeit earlier than expected.

Anyhow, it's nice to see conservative performance projections have been right on the money for Zen5. Luna/Arrow Lake have a good chance to beat it in ST.

 

[adroc_thurston]

AVX-10 is more future proof for upcoming massive parallel designs.

It's literally AVX-512 lowered to 256b native vectors.

 

[soresu]

Not sure how useful it is for consumers outside of PS3 emulation but for the HPC market?

Several software video decoders and encoders use it, and likely a raft of other DCC software bases too.

Don't forget the professional software market exists as well as gamers and HPC.

 

[soresu]

It's literally AVX-512 lowered to 256b native vectors.

Eh?

I thought the point was an SVE like 'write once run everywhere' system where code could either run with 256 bit units on an E core or 512 bit units on the P cores?

(obviously requiring 256 bit instruction parity with AVX 512)

 

[adroc_thurston]

I thought the point was an SVE like 'write once run everywhere'

No.
SVE isn't really that either.
You emit 128b vectors there and off you go.

or 512 bit units on the P cores?

no, you compile to either 256b or 512b target.
256b target doesn't even exist in 10.1 spec, that's later, god knows when, in 10.2.

 

[HurleyBird]

L3 portion looks like it shrunk 1.5 nodes rather than 0.5.

 

[dr1337]

Either AMD marketing team is a bunch of incompetent fools, or AMD as a whole is a bunch of incompetent fools.

More people talking about AMD = better, I don't think they could care less about whatever happens in the internet rumor mill.

What matters is a good product and unless Zen5 actually sucks and cost $999, all of this animosity is gonna be gone by release. I predict a Ryzen 9000 owners thread filled with many happy customers and some people with typical launch bugs. And after about 6 months of that everyone will agree that Zen 5 is good.

 

[Glo.]

I have to say. Looking at where x86 chips are going, I am actually not surprised one bit that Microsoft is showing middle finger and pushing for WoA initiative even harder.

 

[gdansk]

I have to say. Looking at where x86 chips are going, I am actually not surprised one bit that Microsoft is showing middle finger and pushing for WoA initiative even harder.

Qualcomm, MediaTek/Nvidia and AMD have told their plans to Microsoft. They are picking their priorities with a lot more information than we have.
But on the other hand, Microsoft is the company that can't manage to have a moveable taskbar in 2024 so... maybe not the most competent company.

 

[Joe NYC]

AI obviously.

Yeah, so it may be AI inference on the server, where it may get the best usage. AMD had a slide on it in the Turin presentation.

 

[Joe NYC]

L3 portion looks like it shrunk 1.5 nodes rather than 0.5.

Maybe the TSVs were moved from there?

 

[Tuna-Fish]

Maybe the TSVs were moved from there?

If they are using TSMC's latest hybrid bonding, I think for a similar bandwidth connection the TSV area should have shrank by more than half, so that's a contribution.

 

[Saylick]

So I got bored and decided to do a super rough measurement of core areas on STX to try to ballpark the size of Zen 5c vs vanilla Zen 5.

This assumes STX is 225 mm2. Zen 5c is ~ 2/3rds the size of Zen 5 vanilla, including L3 cache. If I try to exclude L3, Zen 5c looks a little denser? Hard to know where L2 ends and L3 begins for those dense cores.

I also measured the NPU (XNDA 2) for fun.

 

[fastandfurious6]

CES'25.

halo and fire range on january 2025??????? why so late

 

[Markfw]

halo and fire range on january 2025??????? why so late

I am going to guess that it has to do with volume, progress and debugging. For example, aside from the AIO, which is different between desktop and server, thr Zen 5 cores are identical except binning IMO. So basically one chiplet and 2 AIO's and a lot of products can come out. Zen 5C is only a small change from Zen 5 core (Identical except cache/speed), and you have 2 complete product lines. And a lot of $$$. The others require a lot more tuning/development/testing.

Please feel free to correct me where I am wrong (nicely)

 

[Ghostsonplanets]

halo and fire range on january 2025??????? why so late

Because Strix Point was pulled ahead to meet MS Copilot + PC push. CES 2025 was the original revised intended target.

 

[adroc_thurston]

CES 2025 was the original revised intended target.

No?

 

[Ghostsonplanets]

No?

When it was? It was supposed to be a early 2024 thing before "plans changed", no?