Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

Does that account for 4 of the cores being zen5c?

8.

So were you wrong or what happened?

You're trying to model PPC out of HMP setup on a non-SIR workload.
Don't.

 

[RnR_au]

Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?

@adroc_thurston has never given us IPC numbers.

 

[uzzi38]

All those references are meaningless since TDP is unknown for all these parts excepted for the 7700X.

Using this CPU as reference and assuming that cores power is 125W then Strix Point has something like 20% better perf/clock if the run was made at 45W, this as an estimation based on power/frequency curves, assuming power scales at an average 2.8 power of frequency between 80 and 125W and 2.36 average between 45 and 80W.

FI computerbase measured the 7700X as 26% faster in Blender than a 7940HS at around 70-90W, their run over 100s display about 85W but Blender test last much more at 800s and they state that the CPU end running at 70W.

If we extrapolate from the Computerbase test, and using the 70W lower bound to not overestimate the calculation, then this Strix Point ES perform 26% better than a 7940HS@70W and about 52% better than a 7940HS@45W, so assuming a run at 45W that would make 1.52x the perf with 1.5x the core count, and this would also imply 20% better perf/clock.

Razer Blade 14 (2023) mit 7940HS und RTX 4070 im Test

Die 3. Generation Razer Blade 14 setzt auf AMD Phoenix und Nvidia Ada Lovelace. Statt 16:9 mit 144 Hz gibt es 16:10 mit 240 Hz. Der Test.

www.computerbase.de

Just pointing out you're assuming the big and little cores are running at the same frequency, but I'd think it's pretty likely that won't be the case. More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets.

 

[PJVol]

More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets

Did I miss something or the L3 and core clocks are now decoupled in Zen5?

 

[Abwx]

Just pointing out you're assuming the big and little cores are running at the same frequency, but I'd think it's pretty likely that won't be the case. More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets.

In full MT using all the cores there s no point in using different frequencies/cores, the most efficient is to to distribute the frequencies evenly.

12 cores running at say 3.8Ghz will be way more efficient than running 4 P cores at say 4.2GHz and the 8 c cores at 3.6GHz for a same throughput, the more the frequency difference between P and c the higher the losses of efficency, only case where this doesnt hold for perfs are games where it can be better to run the main thread at full clock, but then games are unlikely to use 12 cores.

 

[inquiss]

8.

You're trying to model PPC out of HMP setup on a non-SIR workload.
Don't.

Thanks. So strix point is 4+8, kraken 4+4 and halo just flat out 16 ignoring the island? Or is kraken 2+4?

What's Sonoma?

 

[Kepler_L2]

Thanks. So strix point is 4+8, kraken 4+4 and halo just flat out 16 ignoring the island? Or is kraken 2+4?

What's Sonoma?

STX1 4+8
KRK 4+4
Halo 2*8+(4)
SV 0+4

 

[adroc_thurston]

the most efficient is to to distribute the frequencies evenly.

oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.

 

[Markfw]

oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.

I think I understand this. For desktop and HEDT, its all about performance, so everything is Zen5 cores. For laptops, its all about power savings, and since Zen5c has all the same features, it could be 100% Zen5c cores. Servers, I would guess are all one or the other depending on what that specific chip is targeted at.

Personally, I doubt they will be mixed in any config, but we will see.

 

[poke01]

oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.

If they didn’t then there’s no point of having “hybrid” cores. The point of having a P + c is c is much more efficient. One of reasons AMD did is to perform better at a lower TDP.

 

[adroc_thurston]

For laptops, its all about power savings

No. Cost.
Dense is the poverty option.

is c is much more efficient

It's just cheaper rofl.

 

[Gideon]

You're trying to model PPC out of HMP setup on a non-SIR workload.
Don't.

Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger deal

 

[adroc_thurston]

Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger deal.

Man this is the worst attempt to own me in eons.

 

[poke01]

let’s just wait. Less than a month. No point going crazy now.

Also is this the first time of P core and c core SoC from AMD in client?

 

[adroc_thurston]

Also is this the first time of P core and c core SoC from AMD in client?

PHX2 exists so no.
It's the first multicluster HMP tho.

 

[itsmydamnation]

Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?

SPEC INT vs FP.
from what we know 128/256bit FP doesn't see any increase in execution resources AMD is "only" going end to end 512bit , so most of that 20% would be frontend. Bodes well for INT where prefetch/predict/frontend + int execution all see uplifts.

 

[HurleyBird]

oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.

Pretty sure he means multithreaded tasks will perform worse because of synchronization. Which, while theoretically possible, isn't generally the case either.

 

[adroc_thurston]

Which, while theoretically possible, isn't generally the case either.

We're talking Blender, not a particularly high overhead workload.

 

[TESKATLIPOKA]

Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger deal

Your conclusion is based on that Blender result, right?
And you are making a conclusion based only on that?
You know nothing about TDP or clocks of that ES, yet you already make
claims how It's only an incremental upgrade compared to Zen4.
Sorry, but you are making premature conclusions based on a single test without knowing some very important things(TDP, clocks).

 

[Timorous]

Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?

The claim from adroc has always been 1t spec int rate 2017.

This test looks to have been an all core blender test.

They are not the same.

Only when we have 1t spec int rate 2017 results will we be know if the claim was accurate or not.

 

[Abwx]

oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.

If we start from the point of the curves where P and c cores have similar efficency then increasing total throughput by 6.6% by just boosting the 4 P cores frequency accordingly while keeping the c cores at the same frequency will require 16% more power than just boosting all the cores frequencies by 6.6%.

And the more you boost the P while keeping the c cores at same frequency the more this innefficency will increase, if a 13.3% boost is relying exclusively on the P cores then the previous figure will jump to 32% higher power than an all cores 13.3% homogeneous boost.

AMD Unveils Ryzen Mobile 7040U Series with Zen 4c: Smaller Cores, Bigger Efficiency

www.anandtech.com

 

[uzzi38]

Did I miss something or the L3 and core clocks are now decoupled in Zen5?

Well there's two different L3s for each CCX, the main Zen 5 cluster has a 16MB L3, the Zen 5c cluster has an 8MB L3. So the L3 and core clocks don't need to be decoupled in the first place.

 

[uzzi38]

If they didn’t then there’s no point of having “hybrid” cores. The point of having a P + c is c is much more efficient. One of reasons AMD did is to perform better at a lower TDP.

No the whole point of the C cores is to trim on area to just make them smaller, letting them for more of them in a smaller area and make more competitive products for the cloud market. Just like how V-Cache was designed for specific server workloads originally, then it was later realised it could be shipped on desktop as it happened to have a huge uplift on gaming, C cores were originally designed for cloud first, then later brought down to client products to improve competitiveness there as well.

Having a different V/f curve is just a by-product of the sacrifices made to the core to get to that point.

 

[PJVol]

Well there's two different L3s for each CCX, the main Zen 5 cluster has a 16MB L3, the Zen 5c cluster has an 8MB L3

Is this just a guess or is there some slide or whatever that confirms this?

Interesting, if true. Does the 4+4 part also have an "un-unified" L3 ?

 

[LightningZ71]

Unless we've learned something different, the only precedent that AMD has established for combining their P cores and their C cores on the same die, Phoenix2, has a unified L3 for them both.