Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[itsmydamnation]

Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-

4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)

Total 24MB L3 cache

isn't ALLthewatts a weibo that got everything wrong , dissapeared for a few days then re-emerged with a new name?

 

[Joe NYC]

Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-

4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)

Total 24MB L3 cache

According to All The Watts, it is 16MB + 16MB. Is that correct?

https://twitter.com/x/status/1708791849652273180

 

[Tigerick]

According to All The Watts, it is 16MB + 16MB. Is that correct?

https://twitter.com/x/status/1708791849652273180

He followed up the tweet with correction....

 

[Joe NYC]

He followed up the tweet with correction....

I see, thanks.

 

[Tigerick]

But some gossip suggest Zen5 would utilize XDNA2 architecture.

It is not gossip, XDNA2 is indeed comes with Strix Point: Or do you mean Desktop Zen 5???

 

[DrMrLordX]

Namely, with Zen 4 being so strong, what is the reason to release Zen 5?

All AMD has to do is remember the last decade of the x86 PC space to answer that question. Intel rested on their laurels for years, and it fostered an air of organizational complacency which ruined them. AMD suffered a similar setback back in the Hector Ruiz days when they banked on K8 continuing to dominate Intel and their Netburst architecture.

AMD has competition from the ARMy in Apple and Qualcomm, and possibly nVidia.

They can't afford to let up now.

 

[Tigerick]

That's what it supports, but OEM decides what's in there at the end.

ZEN5 is a lot wider than ZEN4, there's a reason it uses 4+8 Design that probably takes the same space as a 8 ZEN5 Design. 50% more L2, 50% more L3, 2 more WGPs that may also be bigger because of RDNA3.5. Probably more/more modern IO (PCIe 5.0?). Bigger AIE. That's a lot to fit in those 47mm^2, don't you think? It's N4 vs N4(P?) after all.

I am more interested on comparison between STX and Qualcomm's X Elite cause they are both launching at the same time and made by N4P process. Surprising, AMD opt for 4P+8E vs Qualcomm's 12 P-cores. Does extra die area give AMD more advantages??

 

[RTX2080]

I am not sure I would call the leaked roadmap "gossip". It has been accurate as far as Hawk Point is concerned.

A leaked roadmap is not as good a source as an official roadmap, but still somewhat above "gossip".

It is not gossip, XDNA2 is indeed comes with Strix Point: Or do you mean Desktop Zen 5???

yeah the source said it would be Zen5 DT having XDNA2 but he then implied it's DT APU having XDNA2, I felt being baited lol.

 

[Thunder 57]

Regarding XDNA, all I have to say to say for now is:

 

[Saylick]

Regarding XDNA, all I have to say to say for now is:

It lets Microsoft market this:

https://www.anandtech.com/show/21207/windows-11-pcs-to-get-microsoft-copilot-key

 

[naukkis]

Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-

4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)

Total 24MB L3 cache

AMD should not be stupid enough to make such a config. I't unbalanced CCX configuration which makes thread scheluding absolutely nightmare as for 5 thread job has to choose core per thread from different CCX:s or switch to low-speed CCX. If they are going to dual CCX-setup they should have used balanced 6+6 configuration and as they went with a such unbalanced I sure believe that they use single CCX-configuration. If their ring is limited to 8 cpu core stops they probably made C-cores to share ring stop leaving c-cores to have less L3-bandwidth in extreme multithreaded situations but that's a far less of a problem that two unequal CCX configuration.

 

[yuri69]

The binutils project got support for Zen 5 as znver5.

There are additional instruction set extensions on top of Zen 4 - AVX_VNNI, MOVDIRI, MOVDIR64B, AVX512_VP2INTERSECT, and PREFETCHI.

• AVX512_VP2INTERSECT is an odd Tiger Lake-specific AVX512 extension.
• AVX_VNNI is a VEX-encoded variant of VNNI introduced by Alder Lake.
• PREFETCHI is a family of PREFETCHIT0/1 instructions introduced by Granite Rapids and later.
• MOVDIRI/MOVDIR64B are instructions for cache bypassing introduced by Tremont and Tiger Lake.

This should bring Zen 5 very close to the Tiger Lake instruction set.

Note, binutils Zen 4 support was added post-relase on 2022-11-15 and the Zen 3 one like 14 days before the launch.

 

[RTX2080]

More intuitive view on AVX512 support:

https://twitter.com/x/status/1743892108962910660

 

[CakeMonster]

I had no idea there were instructions missing from Z4 that were included in Alder Lake (which dropped (but not really) AVX512).

 

[DrMrLordX]

I had no idea there were instructions missing from Z4 that were included in Alder Lake (which dropped (but not really) AVX512).

What's funny is that, according to that chart, the only Intel core with VP2INTERSECT is Willow Cove.

nm it looks like Golden Cove/Raptor Cove has it as well.

 

[JoeRambo]

AMD should not be stupid enough to make such a config. I't unbalanced CCX configuration which makes thread scheluding absolutely nightmare as for 5 thread job has to choose core per thread from different CCX:s or switch to low-speed CCX.

AMD is stupid enough, never doubt it. They disgraced themselves by releasing abomination Threadripper where half of NUMA nodes had no direct connection to memory, so nothing is too stupid for them. There is no redemption for that, straight to hell.

On topic of two different CCX -> it is as bad as any other hybrid, sharing the same L3 cache domain would not add much, while potentially complicating chip design a lot. AMD loves to do these design as lazy as possible, wasn't some chip in the past with laughable on chip layout, full of space?
For intended aplication it would work just fine, 12C of Zen5 is ton of computing and would marketing people will love Cinebench and stuff scores.

 

[igor_kavinski]

On topic of two different CCX -> it is as bad as any other hybrid

Have you seen benchmarks for that yet? I don't think anything has leaked in that regard.

 

[NostaSeronx]

imho, I am hoping for a PHX2 CCX * 2 configuration. That way it scales up from PHX2, rather than being a new paradigm.

CCX0: 2x Zen5 + 4x Zen5c
CCX1: 2x Zen5 + 4x Zen5c

 

[Markfw]

I had no idea there were instructions missing from Z4 that were included in Alder Lake (which dropped (but not really) AVX512).

But what non-server CPUs are in that list ? Zen 4 is the only one unless I missed something.

 

[DrMrLordX]

AMD is stupid enough, never doubt it. They disgraced themselves by releasing abomination Threadripper where half of NUMA nodes had no direct connection to memory, so nothing is too stupid for them. There is no redemption for that, straight to hell.

Oh please, that was one gen of Threadripper and it worked fine anyway. Of all the things a company could do, that's the least of any consumer's worries.

 

[JoeRambo]

Oh please, that was one gen of Threadripper and it worked fine anyway.

I think it was working fine in Cinebench. Anywhere else ran the risk of hitting crazy concurrency problems:

63 Cores Blocked by Seven Instructions

I seem to have a habit of writing about super powerful machines whose many cores are laid low by misuse of locks. So. Yeah. It’s that again. But this one seems particularly impressive. I mean, how …

randomascii.wordpress.com

But i guess it was AMD's way to prepare us all for very parallel future, release as retarded product as possible to exposes such weaknesses before launching 64C chips.

On topic of this new chip -> i don't have any problems with it and it will perform great beyond typical scheduling woes. ZEN5C even with reduced clock is lots of perf.

Still, let's not underestimate AMD's stupidity like @naukkis did, they surely can release lazy and stupid products.

 

[DrMrLordX]

I think it was working fine in Cinebench. Anywhere else ran the risk of hitting crazy concurrency problems:

63 Cores Blocked by Seven Instructions

I seem to have a habit of writing about super powerful machines whose many cores are laid low by misuse of locks. So. Yeah. It’s that again. But this one seems particularly impressive. I mean, how …

randomascii.wordpress.com

But i guess it was AMD's way to prepare us all for very parallel future, release as retarded product as possible to exposes such weaknesses before launching 64C chips.

On topic of this new chip -> i don't have any problems with it and it will perform great beyond typical scheduling woes. ZEN5C even with reduced clock is lots of perf.

Still, let's not underestimate AMD's stupidity like @naukkis did, they surely can release lazy and stupid products.

Only a few people bought those things. And they certainly knew what they were getting into before they bought it.

edit: especially since multiple sites, including Anandtech, reviewed the 2990WX across multiple benchmarks:

The AMD Threadripper 2990WX 32-Core and 2950X 16-Core Review

www.anandtech.com

 

[JoeRambo]

Only a few people bought those things. And they certainly knew what they were getting into before they bought it.

So You are being intelectually dishonest here, going from "worked fine" to 'certainly knew what they were getting into".

 

[moinmoin]

Anywhere else ran the risk of hitting crazy concurrency problems:

Anywhere in crazy Windows scheduler land you mean. All it showcased is how bad and woefully unprepared the Windows scheduler is. You should complain more to Microsoft instead.

 

[Timmah!]

So there goes the presentation and no word of Zen5. Too bad, was looking forward to that. MEH!