Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[A///]

Starfield appears to be heavily memory bandwidth limited, that could be interesting to see on Z5 depending on IF and RAM speeds.

exactly why i asked about the ram.

 

[adroc_thurston]

the 7900xtx was better off as a 7800 or 7800xt.

Names don't matter.

ok and magical ram speeds will be what then?

Same as Zen4 exactly.

 

[A///]

Names don't matter.

it does for marketing purposes.

Same as Zen4 exactly.

pass. if starfield is a taste of what's to come in the future even by better studios that don't have a habit of releasinf bug ridden games the limited bandwidth is a con.

 

[adroc_thurston]

it does for marketing purposes.

No.

if starfield is a taste of what's to come

Also no.

 

[A///]

No.

Also no.

yeah it does. x900 was always a top tier for ati and amd. this last gen was a slap in the face to consumers. I thank @TESKATLIPOKA for questioning the product launch from the get go before it came out based on leaks. the price amd is asking for the 7900xt and xtx is criminal.

it kind of is. you think bethesda is the only studio that's willing to do sloppy work and ask for a lot in return? with game prices going up every few years and code quality going down with serious bugs and issues with game engines it's only a matter of time.

 

[Markfw]

Starfield appears to be heavily memory bandwidth limited, that could be interesting to see on Z5 depending on IF and RAM speeds.

Not to mention timings. Check some of the threads in the Zen 4 build threads. Intel does not seem to be hampered as much in this respect, but all it would take to kill AMD in that comparison is have memory speed, timings and IF speeds all wrong. If we had a benchmark where BOTH were setup correctly, it could be a very different story. Especially with some current BIOS, where memory speed now goes up to 8000 ?

 

[adroc_thurston]

x900 was always a top tier for ati and amd

Navi31 is their top-end offering, yes.

you think bethesda is the only studio that's willing to do sloppy work and ask for a lot in return

Yes, everyone else uses UE5 more or less.

 

[Ajay]

There is in laptops, they need that 1t.

Mobile as in phone and tablets, not Laptops. I mentioned laptops separately.

Apple just can't make their cores go fast; skill issue basically.
They really want to, but they can't.

Hmm, they have lost some top engineers to poaching over the past 5 years. Not sure if that's it. I guess the obs answer is most of their people came onboard to do lower power high IPC, not IBM zoom, zoom (following your fast cpu meme ).

 

[adroc_thurston]

Mobile as in phone and tablets, not Laptops

Yea whatever.

I guess the obs answer is most of their people came onboard to do lower power high IPC

Yea a lot were PA Semi people but still.
Not like Apple cores are that slow, A17 will be like 3.7GHz in a phone.

 

[ozzy702]

Starfield appears to be heavily memory bandwidth limited, that could be interesting to see on Z5 depending on IF and RAM speeds.

I watched that last night which led me to popping in here and seeing what's up. I'm on a 5900X and a 4090 at the moment, I'll probably hold off on buying a new CPU/MOBO/RAM until Zen5 is released. Curious to see if AMD makes meaningful changes.

 

[exquisitechar]

I watched that last night which led me to popping in here and seeing what's up. I'm on a 5900X and a 4090 at the moment, I'll probably hold off on buying a new CPU/MOBO/RAM until Zen5 is released. Curious to see if AMD makes meaningful changes.

Seemingly, no, not until Zen 6.

I hope they enable both GMI3 links on Zen 5 single CCD parts. It's a joke that you can't make use of DDR5's bandwidth with the Zen 4 ones.

 

[A///]

Did papermaster not touch on that around the zen 4 release in an interview with toms or anand?

 

[Ajay]

Seemingly, no, not until Zen 6.

I hope they enable both GMI3 links on Zen 5 single CCD parts. It's a joke that you can't make use of DDR5's bandwidth with the Zen 4 ones.

If I understand the trajectory for Ryzen consumer CPUs is that Zen5 mainly has significant core improvements and Zen6 will have significant uncore improvements. So, we are likely to see more significant bandwidth improvements with Zen6 - though exactly what approach AMD will be taking is pretty much unknown outside AMD aside with the exception of large IHV that need to be developing boards and systems for Zen6 EPYC CPUs well in advance (via simulations).

 

[adroc_thurston]

though exactly what approach AMD will be taking

Client will look like STX-halo, server will be akin to Navi4C.

 

[maddie]

Client will look like STX-halo, server will be akin to Navi4C.

What about the Epyc-X line?

 

[adroc_thurston]

What about the Epyc-X line?

Well you still stack cache on a CCD so not much difference.

 

[Fabius]

Yeah, because as they've been consistently saying on their earnings calls, they're undershipping. They don't want to sell to the client markets while they're as down in the dumps as they are.

Are you trolling? Go see the last 4 quarterly if it is not true that the PC-Client division of AMD is at a loss. As for profits, very few are dividing them.

 

[maddie]

Well you still stack cache on a CCD so not much difference.

Yeah, but only half sized. Assuming they still stack V-cache only over L3, that'll be a big reduction over present products unless they go to 4+ Hi-stack.

 

[adroc_thurston]

Yeah, but only half sized

Que?

that'll be a big reduction over present products unless they go to 4+ Hi-stack.

N3e/p/whatever literally have 0% SRAM scaling off N5.

 

[A///]

Yeah, but only half sized. Assuming they still stack V-cache only over L3, that'll be a big reduction over present products unless they go to 4+ Hi-stack.

This was thought of when the first x3d processors rolled out. TSMC had developed 12 high stacking 1 or 2 years prior to the announcement. The issue with multi stack is you're battling voltages and heat displacement. I'm unsure if tsmc's back space powder delivery may address the voltages issue in future or not. Too many cache layers may impede processor performance by way of clocks through voltage reduction so as not to harm the cache layer.

however it would be interesting if tsmc can package multip varieties of cache on a singular layer and attach it to the other non x3d die.

 

[adroc_thurston]

The issue with multi stack is you're battling voltages and heat displacement

No it's just more cost for little gains.

 

[A///]

No it's just more cost for little gains.

One takes precedence over the other.

 

[maddie]

Que?

N3e/p/whatever literally have 0% SRAM scaling off N5.

Yeah, cache bits on N3 will be same size as N5, so 16MB on N3 = N5, which only have 32MB per V-cache slice. present products have 96MB L3 max, so 3 layers to not be less, unless some new tech possible.

 

[adroc_thurston]

which only have 32MB per V-cache slice

?
V$ tile is still N6 and will be N6 likely forever.

so 3 layers to not be less

It's 1-Hi, 32MB base + 64MB extension and for a while.

 

[maddie]

?
V$ tile is still N6 and will be N6 likely forever.

It's 1-Hi, 32MB base + 64MB extension and for a while.

Zen4 c has 16MB L3
V-cache for that would be 32MB

As cache is area constant now, are you saying that Zen5 c will have 32MB L3 (2X % area of chiplet). This is the only way your server = Zen c and your 32MB + 1 Hi 64MB claims can coexist.