- Mar 3, 2017
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It all depends on the overall package. I'd rather take +35% IPC at 5 GHz than +20% IPC at 5.7 GHz. Which usually means better average power efficiency and more improvements by increasing clock speeds in the future. AMD increased clock speeds with Zen 4 quite substantially. But that's not possible with every generation because you are limited by the available process nodes. That's why you have to do more on the architecture level. And if that means some temporary clock speed regressions then it can be worth it in the long run. I expect Intel to do exactly that with Arrow Lake and successors.
Well the problem here is that it's not 35% ipc uplift it's only 25% at 5.225 Ghz, at least according to the chart anyway.
Why are you talking about +25% IPC gain as if it was a fact? Have I missed something?
Diminishing returns are a thing. You can't expect the same gains every generation.
The IPC increase with a frequency decrease is a GOOD thing. There are limits on frequency where power starts to become a real problem - that's why frequencies haven't been constantly climbing over the years and topped 10 or 20 GHz by now. Intel has done similar retrenchments in the past on multiple occasions where they have done IPC increases that required sacrificing frequency (most notably with P4 -> Core but that's not the only time)
There's a reason why Apple, the IPC leader, has far lower frequencies and its not just because they are targeting lower TDPs. There are design tradeoffs between IPC and frequency that make it impossible for their designs to clock at 6 GHz even if the power budget was unlimited.
As mentioned before I don't expect and frankly don't want a 25% ipc. I'm only react to the chart posted several pages ago.
Well zen has a momentum and it'd be disappointing for an architecture touted as the biggest ipc jump since zen 1 from Excavator and yet the uplift is the lowest in all zen uarch. IPC increase with a reduction in Ghz isn't necessarily a positive sign simply because the performance curve isn't known yet.
However I do get your point and agree with it partially, clock reduction is fine but only when accompanied with a massive ipc uplift like >30%.Amd is on the offense and the conventional wisdom says the attackers needs to be out number the defense by the factor of 3. Regarding only the core, right now AMD is the market leader only core counts and single thread performance, and I feel like Intel will push back on the ST performance sooner than we might expect.
Apple cores aren't that great to be honest considering it's on the latest nodes with a lot of transistors. A fair comparison would be between x86 vs x86 and arm64 vs arm64
No point in talking about Zen 6 being in trouble against Intel's far-off cores when we don't know much about either. In the near future, AMD's competition is Arrow Lake with a projected mere 5-10% performance improvement compared to Raptor Lake refresh.
Really, in light of the meagre improvements brought by Apple's recent cores and Intel's upcoming ones, it seems silly to deride Zen 5 for (maybe) not reaching some arbitrary uplift in ST performance with a 25% increase in IPC and a small decrease in clock speeds. If the usual hype meisters are correct, it's actually better than that, but I'm not holding my breath.
You do know Intel’s LNC is also going to have an even bigger fmax regression right? It’s physics.
Eh, I wouldn’t say they’re leading in 1T perf. It all depends what metric you use to measure it. I would say they’re currently comparable.
The xeons would greatly benefit from the high ipc low frequency uarch for sure, but I don't know how it's relatable to what I'm saying. Forgot to mention right now means Turin sample vs Emeral Rapids.
Honestly the intel projection slides seem off to me. 3 nodes jump with a complete core redesign and the best they can come up with is less than 10% ST? Am I supposed to believe arrow lake will have 40%+ ipc uplift with more than a 1Ghz of clock reduction? How can intel justify the development effort into this thing? I mean sure it's a base for later uarch with rentable units but it still seems very odd to me.
Markfw
Moderator Emeritus, Elite Member
- May 16, 2002
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I saw a benchmark where Emerald Rapids got crushed by Genoa, let alone Turin.
I remember in the P4 days Intel swore up and down they would get to 10+ ghz. They also used that as a reason the keep pushing their hot and power hungry architecture. Ironically today they are closer than ever before, despite having a much wider/faster core.
I have seen no indications of an fmax regression for either company. Further, for Apple, frequencies keep going up. Intel has also seen a pretty decent uplift with Intel 4 (just not 1T clocks, which may or may not be artificially limited for reasons)
I have seen CLAIMS of a regression, but no real evidence to back it up. As I mentioned before, fmax means little these days anyway.
Nah dawg, that ain’t me.I would like to remind us all, that AMD hype trains like to derail themselves after the releases of new AMD hardware.
Lets keep our expectations in check, and don't overthink stuff that is thrown on the internet.
It's the same Intel that spent their resources on Rocket Lake in a desperate attempt to take the lead and failed. When you have no good alternatives, you do the only thing you CAN do, even if it feels like a wasted effort.
It's not 3 node jumps, it's at best advancing things by 1.5 nodes. So far the performance results measured from the A17 on N3B gained 14% more performance in exchange for 35% more power in Specint, while gaining 9% performance for 22% more power in Specfp.
It's on N3B, which currently seems to have the same performance as N4P. I'm attributing some of the poor performance of the A17 to bad yields forcing it to run higher than ideal voltage. I'm assuming that by the time ARL-S comes around yield improves, which is why I'm saying it's basically 1.5 nodes ahead of current Intel 7 instead of just 1. I could make a compelling argument that it is a single node jump from the Intel 7 that's shipping with RPL-R though.
Zen 5 legitimately has the better process tech for this upcoming generation. All things considered I'd take N4P over the early version of N3B that ARL-S is stuck with.
Edit: Changed second image to just SoC power and not motherboard power.
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Frequency has been climbing steadily, but there's a big difference between the designs now and from two decades ago in that a 4 GHz clock speed can be done without needing any incredibly lengthy pipeline.
Prescott (Pentium 4) had around 30 pipeline stages to get to around 4 GHz and some have said Intel had plans to go up to 40 stages to get to 5 GHz before abandoning the idea.
On the flip side, clock rates wouldn't have grown as rapidly if companies hadn't started lengthening their pipelines during the late 90s through the mid-2000s. Both Intel and AMD processors in the early 90s were 5 stage designs. Had they stuck closer to that the frequency ramp would have been a lot more gradual.
But people realized that chasing more MHz was a pipe dream and cooler designs prevailed. Intel cut the pipeline stages in more than half when moving to core and haven't really gone much beyond that since.
I would t be surprised if 10 GHz were achievable if someone were to use a ridiculous 40 stage pipeline design, but it would probably be a hot mess with all the usual downsides of anything with a pipeline that deep. Even today there's probably some fool's who'd line up to buy it because "bigger number = better".
biostud
Lifer
- Feb 27, 2003
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I think AMD is comfortable increasing ST 20-25% pr generation and MT as much as power allows, as it will still be enough for many to upgrade.
This seems like a super rare "off" year for Apple. And as far as I know the CPU isn't changed much in design at all. More of rebranded A16 set of cores taped on N3B.
I'm sure Apple will switch to N3E next year along with everyone else. That being said, if N3B is this bad while being expensive I can see why everyone balked at using it. A rare loss for TSMC as well.
I don’t think switching to N3E is going to fix much. Per TSMC, N3E has 3-8% more performance than N3B. There’s almost no difference between N4P and N3E sans DTCO.
Gate:
N4P - 49nm
N3E - 48nm
N3B - 45nm
Fin:
N4P - 28nm
N3E - 26nm
N3B - 26nm
MMP:
N4P - 28nm
N3E - 26nm
N3B - 23nm
We’ll see how the N3E based silicon turn out but as of now, N3 seems borked.
They could have - they may have even had something able to run at that speed at one time.
P4 was an interesting beast with its large number of pipeline stages with minimal FO4 delay - and especially its double clocked ALU. Successive iterations of P4 expanded the stages that were double clocked, and it was rumored (and seems pretty clearly the case) that their plan was to continue that until whole pipeline was double clocked. Of course at that point you can expose those internal half stages and call your 31 stage pipeline 62 stages. Then the GHz number you claim magically doubles. From the perspective of CPU performance nothing would really be different, but man Intel's marketing team had to be licking their chops for that day since Intel had over a couple decades trained consumers to equate MHz / GHz with CPU performance!
They assumed as they shrunk P4 designs they'd be able to clock it higher and higher to continue down that path, but they kind of hit a wall around 4 GHz. At a certain point in any process as you increase frequency power draw begins to increase asymptotically, but shrinks used to (but no longer were) push back the frequency where that occurred. Consider that overclockers were reportedly exceeding 8 GHz with P4s that were shipped at less than half that frequency. That showed they had a lot of legroom if power wasn't limited - far more than today's CPUs which would have to exceed 12 GHz on LN2 to be comparable!
Now if you consider that poor overclocked and overstressed 8 GHz P4 was internally running some pipeline stages at 16 GHz, Intel kinda sorta reached that goal if you're willing to accept several very large asterisks. Consider that almost two decades later record overclocks have only increased marginally from the P4's 8 GHz to today's 9 GHz - despite far better support of overclocking from both Intel/AMD and motherboard OEMs.
.....
There s much more transistors in current CPUs, that make a big difference, it s not the same to clock 50M transistors (with an external memory controler) at 8GHz and do so with a billion or more...
There s much more transistors in current CPUs, that make a big difference, it s not the same to clock 50M transistors (with an external memory controler) at 8GHz and do so with a billion or more...
Your post belongs in this thread: https://forums.anandtech.com/threads/intel-had-a-7-ghz-cpu-years-ago.2608070/
A smaller and smaller percentage of the total transistors are active in each successive generation of CPU, and power gating is employed now to completely power off unused sections (not just cores but parts of the cache, FP units in integer heavy code, and so forth) which wasn't being done at all back then.
Sure a CPU "core" has more transistors now than it did back then, but if you ignore the cache and especially ignore all the other stuff on the die the number of transistors allocated to the core has only increased by a single digit number. A17 may have 19 billion transistors, but I doubt one of its big cores has anywhere near even 10x the transistors of a P4 core.
IIRC the decoder in GLC is power gated like 80% of the time.... though I wonder what applications they are using to get that figure lol
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