Okay full speculation/rumor/ugh:
On 22FDX: Geode One and Sempron One => Only SoC(BGA) specification as far as I can tell.
On 12FDX: FX and Sempron => 12FDX CPU/APU(FX unlocked cTDP(25W+) and Sempron locked cTDP(<25W)) appears to have Socket specification.
New architecture: (Geode/Sempron aka 22FDX variant)
Two CPU processors:
1 MB L2 private(2 x 512 KB)
2 MB L3 shared(2 x 1 MB(2x 512 KB?))
Two CU GPU(same as Bhavani/Beema/Mullins/Carrizo-L/Mendocino/Raphael)
12FDX variant hasn't been revealed yet but is mentioned in Personal Computing Return Plan by GlobalFoundries.
- I don't know the exact processor count or GPU count for 12FDX (final track height selection by GF hasn't been leaked so I can't even guess)
FX will replace Ryzen stuff, also brings in a cheaper AM4 socket. I want to iterate that it is more closely related to 25W AM1 rather than 220W AM3+. Sempron replaces prior Athlon 200G/300G/3000G/stuff at lower TDPs.
AMD is moving 14nm products to Samsung to fit in NTO products at Malta (22FDX/12FDX).
*Architecture should be Zen3/Zen4 FPU but with Integer/General Purpose-added:
2. Mapper/NSQ (Load/Store into PRF occurs here)
3. Two Schedulers: Grid-capable (load two superscalar instructions as one 128-bit SIMD)
4. Two Execution Clusters: 128-bit depth (2x64-bit/1x128-bit :: not sure if 4x32-bit got in first gen(22FDX) or improved gen(12FDX))
VALU0 (iCluster ports 0,1)
VALU1 (iCluster ports 2,3)
VAGU0(iAGU0+iAGU1: iCluster ports 4,5)
ISA and ISE executes on the same datapaths rather than seperate ones.
A single-thread can use both clusters:
VALU0/1 in P0/P1/P2/P3 => 8x ALUs for a single thread. <== only possible in loops (via micro-op cache)
Same units available in 2x Puma FPU configured into a SMT-style processor. Just another way of doing Zen architecture for GlobalFoundries.
Zen1 => 4x ISA 64-bit &&(and) => 3x ISE 64-bit
XV/JG => 2x ISA 64-bit &&(and) => 2x ISE 64-bit
Whereas this architecture => 8x ISA 64-bit ||(or) => 8x ISE 64-bit
22FDX is not AM4 standard but could pop-up if AM4e (stoney ridge's socket) makes an appearance. However, it is better to expect AM4b with reduction of VRM capacity and removal of Chipset I/O Hub. With that using a shrinked and more capable version(loops-limitation removed?) of the 22FDX design.
- Cheaper node(FDX)/processor(area-shaved)
- Cheaper AM4 variants(reduced BOM w/ AM4+ boards; AM4b: reduced VRM/no chipset, AM4e: reduced 128-bit DDR to 64-bit DDR, only a single PCIe x4 slot)
Also, 22FDX might launch after 12FDX parts. So, sorry for putting it first, but it was the actual origin node for the new stuff. However, the node hasn't hit its highest performance node variant. For example: AMD didn't do 28HP in 2012 or 28HPP in 2013... they did GF28SHP(for High-end) then did GF28A(for Low-end). 12FDX unlike 22FDX is launching in its highest performance state from the get-go. Only minor refreshes are needed in 12FDX like GF28A in Bhavani(v1) -> Carrizo(v2) -> Bristol(v2.1) -> Stoney(v2.2) -> Stoney Refresh(v3) -> Stoney Refresh2(v4: unreleased A9-9435/A6-9235). Of which, Geode for 12FDX is launching at the end of 12FDX where transistor optimization is best.
12FDX Demo/Launch/Release => July 2023+
22FDX Release => January 2024+
FX should follow suit of Raphael having an integrated GPU, but should be "monolithic." The internal codec isn't based on VCE/VCN(Custom Cadence Xtensa) but rather Xillinx's Media Accelerator:
AVC, HEVC, VVC (<== customer might need to pay for license to use these)
VP8, VP9, AV1 (<== free for customer use)