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The new AMD Picasso APU appears in the UserBenchmark database

NTMBK

Diamond Member
Nov 14, 2011
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Meh, it's just a Raven Ridge clock bump. Hardly exciting.
 

piesquared

Golden Member
Oct 16, 2006
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Meh, it's just a Raven Ridge clock bump. Hardly exciting....to me
Fixed. That is obviously just your opinion.

We don't know what it is. And even if it is a clock speed bump with absolutely no other improvements i think it would still be a nice improvement given that Raven Ridge is already the best mobile x86 processor available. However it is highly unlikely that it will only be a clock speed bump without any other tweaks to increase efficiency and performance.
 

rainy

Senior member
Jul 17, 2013
453
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Meh, it's just a Raven Ridge clock bump. Hardly exciting.
I don't think so: I presume that Picasso will share similarities with Matisse (Ryzen 3xxx series) in similar fashion to Raven Ridge which have more common with Pinnacle Ridge rather than Summit Ridge.
 

NTMBK

Diamond Member
Nov 14, 2011
9,188
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I don't think so: I presume that Picasso will share similarities with Matisse (Ryzen 3xxx series) in similar fashion to Raven Ridge which have more common with Pinnacle Ridge rather than Summit Ridge.
Nah. Ryzen 3xxx is going to be 7nm, Zen2 cores. As per the article, Picasso is "Raven Ridge architecture", i.e. a clock speed bump.
 

Olikan

Platinum Member
Sep 23, 2011
2,003
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Raven ridge with pinnacle ridge goodies (IMC, faster L3 cache, and xfr2) are welcome changes... But i hope there is more...

Vega igp on 12nm will be interesting
 
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whm1974

Diamond Member
Jul 24, 2016
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Raven ridge with pinnacle ridge goodies (IMC, faster L3 cache, and xfr2) are welcome changes... But i hope there is more...

Vega igp on 12nm will be interesting
OK why wouldn't AMD have next years Picasso APU on 7nm process? That makes more sense to me then 12nm.
 

PeterScott

Platinum Member
Jul 7, 2017
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OK why wouldn't AMD have next years Picasso APU on 7nm process? That makes more sense to me then 12nm.
A new tapeout including all the masking layers is VERY expensive.

It can make sense to milk the current masks for all they can, especially since the ASP on RR is not that great, since it is considered a budget part.

A 12nm APU, would just be Raven ridge with the same process refinements that Ryzen got, which means exactly the same RR die, just with a bit more clock speed. But it would have none of the costs of a new tapeout. So huge cost saving for AMD.
 

whm1974

Diamond Member
Jul 24, 2016
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A new tapeout including all the masking layers is VERY expensive.

It can make sense to milk the current masks for all they can, especially since the ASP on RR is not that great, since it is considered a budget part.

A 12nm APU, would just be Raven ridge with the same process refinements that Ryzen got, which means exactly the same RR die, just with a bit more clock speed. But it would have none of the costs of a new tapeout. So huge cost saving for AMD.
Ah I see now. Thanks for explaining.
 

PeterScott

Platinum Member
Jul 7, 2017
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Though I would add, 12nm RR, is not terribly exciting either.

The real excitement is what happens with Zen 2, IPC boost? Clock speed boost? Core count boost? If so how, more CCXs, or CCX with more cores.

Zen 2 is catnip. :D
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,222
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I don't think Picasso will be based on Raven Ridge much.

Speculation:
ZenC + VegaC => Zen-Compact and Vega-Compact which utilizes 12LP 7.5-track lib.

Going further Picasso will split:
Dali on 12FDX w/ a ~50% cost reduction (Vega?)
Renoir on 7LP-EUV w/ a ~50% performance increase. (Navi?)

12FDX and 7LP-EUV both however got a delay till mid-2020. So, I am not sure...

Picasso/22FDX sku => October 2018-Feb 2019
Picasso+/22FDX sku+ => October 2019-Feb 2020
Renoir/Dali => October 2020-Feb 2021

The Value roadmap for AMD is undisclosed and so is the Fenghuang/Mystic Bird roadmap.
Enthusiast => xPU which is based on CPU and GPU separate on same package.
Performance => APU roadmap with Raven Ridge -> Picasso -> Renoir.
Value => APU roadmap with Bristol/Stoney -> 22FDX -> 12FDX.
The mainstream category is undecided currently if AMD wants to do CPU+GPU xPU with the FDSOI node. This would technically compete with the performance line. So, it most likely has been dropped or is in limited dev for low-cost semi-custom.
 
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PeterScott

Platinum Member
Jul 7, 2017
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It literally says "Raven Ridge architecture" on the slide.
Exactly.

Summit ridge + Process Refinement == Pinnacle ridge
( -- Lag --) Raven Ridge + Process Refinement == Picasso

Picasso is just process refinement for Raven Ridge. They are not designing a new APU on 12nm, and a 7nm APU will significantly lag 7nm Ryzen desktop/TR/Epyc.
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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It literally says "Raven Ridge architecture" on the slide.
For that slide, the uplift isn't comparable to that of Pinnacle Ridge.
-> PR: Performance Uplift
-> PC: Power/Performance Uplift.

The Raven Ridge that launched was the oops version/B revision. So, Picasso could actually be much closer to the original Raven Ridge concept. The APU side doesn't always follow the CPU side @ AMD. So with Picasso, it starts to diverge into its niche of optimizations.

There is also Picasso launching on top of River Hawk(10W-35W) 7-nm vs Horned Owl(15W-65W) 14-nm. So, Picasso to achieve the same amount of capabilities requires much more extensive changes. Hence, why Picasso != Raven Ridge.
 
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CatMerc

Golden Member
Jul 16, 2016
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For that slide, the uplift isn't comparable to that of Pinnacle Ridge.
-> PR: Performance Uplift
-> PC: Power/Performance Uplift.

The Raven Ridge that launched was the oops version/B revision. So, Picasso could actually be much closer to the original Raven Ridge concept. The APU side doesn't always follow the CPU side @ AMD. So with Picasso, it starts to diverge into its niche of optimizations.

There is also Picasso launching on top of River Hawk(10W-35W) 7-nm vs Horned Owl(15W-65W) 14-nm. So, Picasso to achieve the same amount of capabilities requires much more extensive changes. Hence, why Picasso != Raven Ridge.
What do you mean by oops version/B revision?

Other than that I agree. The 7.5T libraries on 12nm offer 16% lower power at the same frequency, and the leaked slide mentioned performance AND power uplifts, where as Pinnacle Ridge was listed as performance only.

I expect Raven Ridge 12nm with a new layout taking advantage of 7.5T libraries.
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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What do you mean by oops version/B revision?
The original version of Raven Ridge is Quad-core w/ 8 MB L3 cache and a 12 CU iGPU. There is also the Raven Ridge A2 which had a 16 CU iGPU with a single HBM stack. We should only focus on the A1, and not on the A2. The yields and performance between CPU and GPU with the 8 MB L3 and 12 CUs weren't good. So, AMD re-taped out Raven Ridge without those deterrents, hence the Raven Ridge delay.
 

CatMerc

Golden Member
Jul 16, 2016
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The original version of Raven Ridge is Quad-core w/ 8 MB L3 cache and a 12 CU iGPU. There is also the Raven Ridge A2 which had a 16 CU iGPU with a single HBM stack. We should only focus on the A1, and not on the A2. The yields and performance between CPU and GPU with the 8 MB L3 and 12 CUs weren't good. So, AMD re-taped out Raven Ridge without those deterrents, hence the Raven Ridge delay.
Doesn't seem very plausible. If the yields were poor they'd just cut down the parts, very much like they do now on mobile. At AMD's volumes that is more financially sound than creating new masks.
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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Doesn't seem very plausible. If the yields were poor they'd just cut down the parts, very much like they do now on mobile. At AMD's volumes that is more financially sound than creating new masks.
AMD releases RRA1. It is found out best SKUs are salvaged parts. Media does _____ , consumers expect _____ to be down. Somethings are best not released, like the 6-core GDDR5 Hi-End 2014 APU. 4 MB L2 and 2 CUs on RRA1, I'm pretty sure the iGPU would have actually cutted a complete array. So, even less would be in the 2700u part. So, instead of 11 CU to 10 CU, it would be 12 CU to 8/9 CUs. So, it was in AMD's best interest to keep up their REP.

Picasso is on top of the 7nm APU spot. (River Hawk and 7nm DUV SKU)
Picasso is launching around Intel's 2019 SKUs. (I have to delve into that, 2019 is apparently going to do something for Intel on 14nm)

Picasso has been uplifted in the SoC projects to encompass more enthusiast features for higher ASP. So, the things skipped over is ported above Raven Ridge to Picasso. Which then would have higher yields and new tools at a later date.

RR => $169 for ~210 mm squared
PR => $299+ for ~210 mm squared <-- Picasso imho needs to achieve this.
 
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CHADBOGA

Platinum Member
Mar 31, 2009
2,040
699
136
Fixed. That is obviously just your opinion.

We don't know what it is. And even if it is a clock speed bump with absolutely no other improvements i think it would still be a nice improvement given that Raven Ridge is already the best mobile x86 processor available. However it is highly unlikely that it will only be a clock speed bump without any other tweaks to increase efficiency and performance.
How well is this "best mobile x86 processor available", selling?
 

AtenRa

Lifer
Feb 2, 2009
13,571
2,604
126
A new tapeout including all the masking layers is VERY expensive.

It can make sense to milk the current masks for all they can, especially since the ASP on RR is not that great, since it is considered a budget part.

A 12nm APU, would just be Raven ridge with the same process refinements that Ryzen got, which means exactly the same RR die, just with a bit more clock speed. But it would have none of the costs of a new tapeout. So huge cost saving for AMD.
I dont believe they can use the same masks from 14nm to 12nm.
 

NTMBK

Diamond Member
Nov 14, 2011
9,188
2,472
136
I dont believe they can use the same masks from 14nm to 12nm.
Isn't that what they did from Summit Ridge to Pinnacle Ridge? Same masks, some transistor performance improvements, and some microcode improvements to fix XFR.
 

CatMerc

Golden Member
Jul 16, 2016
1,114
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Isn't that what they did from Summit Ridge to Pinnacle Ridge? Same masks, some transistor performance improvements, and some microcode improvements to fix XFR.
Aren't the same masks. Way too many changes on the process front to just copy paste the masks. The fin shape changed, the eSiGe trenches are buried deeper, etc'

AMD saved money on reworking the die with the new libraries, but they still had to make new masks.
 

AtenRa

Lifer
Feb 2, 2009
13,571
2,604
126
Isn't that what they did from Summit Ridge to Pinnacle Ridge? Same masks, some transistor performance improvements, and some microcode improvements to fix XFR.
I believe they need new masks for BEOL since that is what they focused optimising in 12nm vs 14nm.
 
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