Review 'The Microsoft Surface Laptop 3 Showdown: Amd Picasso vs Intel Ice Lake' - Anandtech

[RetroZombie]

I don't think you grasp exactly what may be the issue here. In the case of the 3900x and 3950x, the two-chiplet solutions simply doubled the memory write speed of the CPU vs. single-chiplet Matisse running the same memory speed/timings.

Have you ever stopped to wonder why the memory controller on Matisse works that way? What if the memory controller on Renoir doesn't work that way?

Since its a redesign of the layout, if anything I expect them to have a 6 or 8 core monolithic die.

It's 4 or 8, 6 would be a major revamp.
But why don't they pick the Raven Ridge design remove the cpu cores from it and add one or two chiplets to it, wouldn't that be great for desktop/oems market at least, even if mobile not much?
It would not even compete with the others (3200G/3500G) already in the market.

 

[uzzi38]

It's 4 or 8, 6 would be a major revamp.
But why don't they pick the Raven Ridge design remove the cpu cores from it and add one or two chiplets to it, wouldn't that be great for desktop/oems market at least, even if mobile not much?
It would not even compete with the others (3200G/3500G) already in the market.

No. They're not doing any chiplet APUs for a while.

APUs are mobile focused, desktop gets the scraps later on. AMD don't care about the desktop APU market even half as much as the laptop one.

 

[RetroZombie]

No. They're not doing any chiplet APUs for a while.

APUs are mobile focused, desktop gets the scraps later on. AMD don't care about the desktop APU market even half as much as the laptop one.

Yeah I agree which is weird. Maybe they don't wan't products that would compete/compare with the consoles chips...

 

[uzzi38]

It's just not as profitable a market honestly. They'd rather you bought a dGPU to go with.

Use cases for high power iGPUs on desktop are significantly smaller on desktop than on mobile.

 

[jpiniero]

It's 4 or 8, 6 would be a major revamp.
But why don't they pick the Raven Ridge design remove the cpu cores from it and add one or two chiplets to it, wouldn't that be great for desktop/oems market at least, even if mobile not much?

They need something like EMIB or Foveros to do it because the GPU is much more affected by latency.

 

[uzzi38]

They need something like EMIB or Foveros to do it because the GPU is much more affected by latency.

What you're referring to is SoIC, and it'll get used relatively soon, though is nowhere close to the consumer market. More for hyperscalers for now.

Not that it's an issue anyway, GPU chiplets care about latency when we're talking about multiple GPU chiplets, for just one his idea is fine. The bigger issue is just idle power draw makes it unsuitable for mobile, and AMD aren't bothered with creating APUs targetting desktop specifically.

 

[jpiniero]

What you're referring to is SoIC, and it'll get used relatively soon, though is nowhere close to the consumer market. More for hyperscalers for now.

What I mean is that without something like an Active Interposer or EMIB you need the GPU to be on the same die as the memory controller (and possibly more of the IO). At that point the benefit of separating out kind of dies off and you may as well go monolithic.

 

[uzzi38]

What I mean is that without something like an Active Interposer or EMIB you need the GPU to be on the same die as the memory controller (and possibly more of the IO). At that point the benefit of separating out kind of dies off and you may as well go monolithic.

Nah, not really. He's suggesting something like Matisse, but with a few Vega CUs in the I/O die.

And again, for that SoIC exists, and AMD are very keen to use it. In fact, afaik they're leading the charge to use it on TSMC's process anyway. Just, it's for hyperscalers first.

 

[uzzi38]

Btw, Matisse with a few Vega CUs in the I/O die is precisely what I expected Renoir to be for a while a few months ago, but as it turns out, it's not. It would be a pretty cool idea, it's just not happening any time soon.

 

[RetroZombie]

Nah, not really. He's suggesting something like Matisse, but with a few Vega CUs in the I/O die.

Yeah right. But before was suggesting an complete SoC with the possibility to add one CCD to it.

 

[uzzi38]

Yeah right. But before was suggesting an complete SoC with the possibility to add one CCD to it.

That sounds like it'd be NUMA to me, so bad idea imo.
The CCD would have higher latency than the rest of the SoC.

 

[DrMrLordX]

But why don't they pick the Raven Ridge design remove the cpu cores from it and add one or two chiplets to it, wouldn't that be great for desktop/oems market at least, even if mobile not much?

That would probably increase base (read: idle) power draw versus a stricly-monolithic design. Bad for the laptop segment.

 

[IntelUser2000]

That would probably increase base (read: idle) power draw versus a stricly-monolithic design. Bad for the laptop segment.

If its for the desktop segment like he says only then it probably makes sense. The question is whether Renoir is flexible enough to do that. Because they'll need to have 3 different chips(not to mention the various core configurations).

1. Desktop/Server without iGPU and MCM
2. Desktop APU with iGPU/IO on a separate die
3. Mobile APU that's monolithic

It looks like they are not easily amenable to making different dies as Intel's Core chips, and dual core APU dies are just two core disabled versions of the base quad core chip.

Skylake for example has 5 different dies just for client. While it isn't exactly cut and paste, everything is arranged in a way so it can be easily cut at the schematic level to make different configurations. Ring and Mesh IO both contribute to making it easier. Even their graphics cores emphasize greater scalability every generation.

Then again, Intel owns fabs and their dual cores probably ship in the dozens of millions of units every quarter so they have every reason to make it as scalable.

1.7w seperates the two during the anandtech battery test. That's all out takes to post crap run time numbers on these light use tests

It'll be good if they can do it but 1.7W is not a small amount to cut.

It's also not just about idle power, while very important. Icelake XPS achieves amazing idle battery numbers, but at load its worse than Cometlake: https://www.notebookcheck.net/Hot-I...op-Review.434484.0.html#toc-energy-management

*I also question the way sites like notebookcheck uses AC power numbers to compare battery life. Anandtech actually does it the correct way, by measuring battery discharge. You can see from calculating the 7390 2-in-1 discharges at a rate of 1.4W while power consumption measured is at 3W. Clearly not the same thing.*

My guess is that its easier to knock off Icelake systems from the ultra low idle power state, or that its having a harder time transitioning between idle and load states as readily. Whether its a fundamental issue or due to being a brand new platform in 4 years(Skylake forever!), I don't know.

The difficulty is actually achieving better battery life, rather than good numbers on some contrived benchmark tests, like the idle-only test.

We know Intel can do much better. ARM WoA systems get 30-50% better per watt-hour of battery.

 

[naukkis]

It'll be good if they can do it but 1.7W is not a small amount to cut.

Picasso uses regular DDR4 @1.2v, IceLake LPDDR4x @0.6v. AMD does only need to also support lpddr to have similar idle power. And at heavier use that memory power delta increases, so even load power is handicapped pretty badly because of standard desktop memory.

 

[uzzi38]

Picasso uses regular DDR4 @1.2v, IceLake LPDDR4x @0.6v. AMD does only need to also support lpddr to have similar idle power. And at heavier use that memory power delta increases, so even load power is handicapped pretty badly because of standard desktop memory.

They will support LPDDR4X (up to 4266mhz), but it's only enough to shave off about 0.8W of power. They need to work on power management a lot as well.

 

[IntelUser2000]

Picasso uses regular DDR4 @1.2v, IceLake LPDDR4x @0.6v. AMD does only need to also support lpddr to have similar idle power. And at heavier use that memory power delta increases, so even load power is handicapped pretty badly because of standard desktop memory.

Oh boy.

The voltage reduction isn't uniform, its only for certain parts.

https://images.anandtech.com/doci/11021/lpddr4x.png

The main advantage using LPDDR standards for laptops is for modern standby, because it reduces it to 1/7th. When the base platform is efficient its worth it to use LPDDR, but if its not it'll take a lot less proportion of it and may not be worth doing it for the extra cost and complexity.

LPDDR3 vs. DDR3L: Understanding the Differences | Synopsys Blog

Dive into the technical nuances between LPDDR3 and DDR3L memory types and their impact on device performance.

blogs.synopsys.com

Memory is a tiny portion of idle power use.

【後藤弘茂のWeekly海外ニュース】 Ultrabookのアイドル電力消費を100mW以下にするHaswellの省電力技術

The far left of the chart named "RTD3" is when they were aiming for the whole thing to be 100mW. Again the dark orange section which is Memory power stays about the same across multiple power states.

They will support LPDDR4X (up to 4266mhz), but it's only enough to shave off about 0.8W of power. They need to work on power management a lot as well.

Maybe under *some* load conditions. But on idle it's a lot less. On the Haswell presentation, the S0iX state was showing 13mW for the LPDDR3 memory. 13mW x 10 = 130mW, which will significantly reduce modern standby battery life if you used regular DDR3. But it doesn't matter if your system doesn't support it.

Here it's showing even older LPDDR1 and DDR2/DDR3 don't even use 500mW on load!

How Much Power Will a Low-Power SDRAM Save You? — Denali Software (a Cadence company) Technical Article | ChipEstimate.com

PC DRAM chips are the DDR1, DDR2 or DDR3 parts that are used in There are two types of DRAM chips commonly used in embedded systems.almost all PCs and servers. Low-Power DRAM chips are the LPDDR1 and LPDDR2 parts used most often in cell phones and portable applications.

www.chipestimate.com

Choosing between DDR4 and HBM in memory-intensive applications - Tech Design Forum Techniques

Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.

www.techdesignforums.com

5pJ/bit for regular DDR4, or 2W under load with dual channel DDR4-3200.

Lower power memory is only one part of the many equations they need to solve.

 

[naukkis]

Idle power for Intel systems is comparable to Picasso if used with regular DDR4.

And those memory chip power estimations are per chip. To get 128bit memory channel you need at least eight of them. With 500mw per device that makes 4w.

Picasso is very power efficient but using regular DDR4 as memory handicaps it quite a bit - but Renoir will fix that.

 

[mikk]

Idle power for Intel systems is comparable to Picasso if used with regular DDR4.

No, AMD uses more idle power when both have DDR4. It's one of AMDs biggest issues for mobile since Raven Ridge.

 

[RetroZombie]

Finally some of the things I have been saying someone bothered to test:
AMD APU found in macOS Catalina 15.2 Beta?
The tests are in youtube videos at the end from Pro7913 post.

What I expected, the Intel cpu can't be:
- Very efficient aka long battery life when doing stuff
- Very good performance (of an 45W cpu) and simultaneously have the power consumption of one 15W cpu
- Intel GPU performance tanks below the 25 Watts TDP

Also Apple using Amd, many sites already reporting it, that was unexpected.

Another point being the chip monolitic, is it expected the memory latency to improve, and also cpu performance versus matisse?

I'm surprised how few leaks we have for renoir, is the chip still far from release? no certain for the number for the cpu cores nor for the gpu cores, vega or rdna.

 

[Gideon]

No, AMD uses more idle power when both have DDR4. It's one of AMDs biggest issues for mobile since Raven Ridge.

With Raven Ridge yes, with Picasso, it really depends on the laptop. Ironically, despite all the claimed "optimizations" Microsoft actually did quite poorly with the Surface on the idle power compared to some Lenovo laptops. Probably because it's really been built for Renoir. In this post I listed some Lenovo AMD laptops (compared to Intel counterparts) that did quite well in Idle tests. E495 in particular, compared to E490 (links to review in the post).

As you can see both the idle and load metrics are all over the place, depending on the model

I mean just compare the Surface Laptop review numbers to the E495 ones.

E495 draws between 4.1 - 6.3W with 5.86W being the average on idle.
Surface laptop numbers are 3.3 - 7.2W with the average of 7.1W. While the minimum is better the average is considerably worse than it could be.

EDIT:
And the E495 (E495-20NE000JGE) actually lasts 2% longer than the E490 ( E490-20N8000RGE) in the wifi test. Same battery, similar chassis both over 8h, so no slouch.

 

[DrMrLordX]

I'm surprised how few leaks we have for renoir, is the chip still far from release? no certain for the number for the cpu cores nor for the gpu cores, vega or rdna.

Pretty sure Renoir is supposed to be Vega. We'll see. As for release . . . I think Picasso hit store shelves in February of this year. Unless AMD suffers major wafer shortages or some other setback, I would expect a Feb/March release for Renoir in 2020.

 

[uzzi38]

Renoir is Vega, Van Gogh is Zen 2 + RDNA2

 

[naukkis]

With Raven Ridge yes, with Picasso, it really depends on the laptop. Ironically, despite all the claimed "optimizations" Microsoft actually did quite poorly with the Surface on the idle power compared to some Lenovo laptops. Probably because it's really been built for Renoir. In this post I listed some Lenovo AMD laptops (compared to Intel counterparts) that did quite well in Idle tests. E495 in particular, compared to E490 (links to review in the post).

E495 draws between 4.1 - 6.3W with 5.86W being the average on idle.
Surface laptop numbers are 3.3 - 7.2W with the average of 7.1W. While the minimum is better the average is considerably worse than it could be.

E495 uses only single channel memory. Remove other dimm for Surface Laptop and idle power should be similar.

 

[Abwx]

Comparison of ICL, CML and Picasso at Computerbase.de.

At full power perfs are about the same for all CPUs, overall efficency of the three CPUs is even, but ICL consume so much for so smaller frequency that i wonder if there s not a technological shenanigan from Intel, this would explain both the power comsumptiopn and the apparent inability to clock higher than 3.9 GHz...

AMD Picasso vs. Intel Ice Lake vs. Comet Lake

Ende 2019 wetteifern drei CPU-Architekturen um den Zuschlag im Ultrabook: Intel Ice Lake und Comet Lake sowie AMD Picasso. Ein Vergleich.

www.computerbase.de

 

[RetroZombie]

ICL consume so much for so smaller frequency that i wonder if there s not a technological shenanigan from Intel

That's what I have been saying all the time here and thanks for the link.

The author of the review (translated) speaking about the (anandtech) review:

"The test is interesting, but many tests seem to me to be very short. In addition to such benchmarks (see the standard course with a 17 percent lead Ice Lake on Picasso), I also looked at other scenarios, where Picasso suddenly has the upper hand."

From one of the posters:

As a non-enthusiast, you can see the beautiful colorful benchmark bars on the Internet, which show Intel everywhere in front, and in practice it's just not true.