[Techpowerup] AMD "Zen" CPU Prototypes Tested, "Meet all Expectations"

[Fjodor2001]

For a lot of people, these improvements will be a big deal.

In what way?

It's going to be great for a 2017 15-inch MacBook Pro, 21.5-inch iMac (and maybe even entry level 27-inch iMac), and it could even enable some pretty thin-and-light gaming capable PCs that don't require low-end discrete GPU. As these iGPUs get better, they will become less niche

Still niche products.

I'm not so sure.

Ok, so what CPU performance improvements do you expect from KabyLake over Skylake?

 

[Arachnotronic]

Is this enough to make it "the greatest chip" intel ever produced - in your interpretation of the words?

Well it depends on who's asking!

I would argue that Haswell was a huge leap forward because it literally enabled all day battery life in slim, fast notebooks like the MacBook Air. Skylake is a big deal because Intel is doing deeper levels of platform integration, and they are doing what is essentially a "server specific" CPU core for Xeon E5/E7.

Battery life in video playback also went up nicely because Intel's media decode engine no longer totally sucks as it did in prior gen chips. If your thing is high quality video playback with great battery life, Skylake might be Intel's "greatest chip" to you.

If your workload is HPC and you can compile your code to take advantage of AVX3, you might find Skylake Xeon to be the "greatest chip" Intel has ever produced.

For me personally? Skylake on desktop wasn't the biggest improvement I've experienced, but it is a solid performer and I enjoy it very much.

Skylake-E might be in the running for "greatest chip" for me as a performance desktop enthusiast; we'll see how it overclocks, what core counts Intel offers, and so on.

 

[Arachnotronic]

In what way?

Longer battery life while playing videos, more robust mobile gaming capabilities (especially if you are using a GT4e in a notebook or something like a NUC), etc.

Still niche products.

iMac is niche? Could have fooled me.

Ok, so what CPU performance improvements do you expect from KabyLake over Skylake?

I don't know yet. When/if I find out, I will share.

 

[cytg111]

It's really hard to disagree with this statement. Skylake brought a big boost in 3D graphics, media encode/decode (Haswell/Broadwell sucked at this), integrated an ISP into the main die (first for a Core-class PC processor), and obviously CPU performance went up nicely. Oh and the packaging job they did on Core M Skylake was awesome (very small package, dies very tightly packed together) particularly for tablet-like form factors.

Skylake, when taken as a total package, was a pretty big jump gen/gen. Just because all you focus on is CPU performance in high power envelopes doesn't mean that this is what Intel execs are referring to.

- Media encode/decode : Nice to have, sure, but nothing that I allready cant do on the CPU right?
- ISP ? Nice for a tablet i guess
- CPU performance went up nicely. Did it? Debateable I guess. highspeed DDR4 may have an impact though.
- packaging job they did on Core M Skylake was awesome : Dont care.

Summing up with my notes; they got it crammed down to broadwell wattage levels (or clocks up to haswell levels), upgraded som hardware pathways for mediaencode and crammed a camera in.

I dont see it.

 

[mysticjbyrd]

What happened to Zen talk?

 

[mysticjbyrd]

I don't know yet. When/if I find out, I will share.

Wouldn't the fact they are working on integrated graphics on Kaby Lake suggest they can't really squeeze out much more performance on this node? The only reason Kaby lake will even exist is because cannonlake was delayed.

I personally don't expect much on the desktop PC side of things.

 

[cytg111]

I would argue that Haswell was a huge leap forward because it literally enabled all day battery life in slim, fast notebooks like the MacBook Air.
- Like broadwell core-m ?

Battery life in video playback also went up nicely because Intel's media decode engine no longer totally sucks as it did in prior gen chips. If your thing is high quality video playback with great battery life, Skylake might be Intel's "greatest chip" to you.
- There is that, surface pro got a little better.

If your workload is HPC and you can compile your code to take advantage of AVX3, you might find Skylake Xeon to be the "greatest chip" Intel has ever produced.
- I am sure we are not debating the serverline here, but we could be how avx3 was pulled from the desktop part last minute..

For me personally? Skylake on desktop wasn't the biggest improvement I've experienced, but it is a solid performer and I enjoy it very much.

Skylake-E might be in the running for "greatest chip" for me as a performance desktop enthusiast; we'll see how it overclocks, what core counts Intel offers, and so on.
- Running quad DDR4 could be interresting, sure.

I am at the same conclusion as before, with all the great ones in the bag for intel, how some of you guyes insist skylake being the best ever of all time .. insisting on climbing that tree and defending the position to no end.

 

[DrMrLordX]

What happened to Zen talk?

I think we ran out of substantive things to say about Zen some time ago. Need moar data.

 

[bystander36]

It isn't?

What chip has been more important?

In the last decade, I'd say Nehalem was the most important. Everything else has been building on that.

 

[mysticjbyrd]

I think we ran out of substantive things to say about Zen some time ago. Need moar data.

This is why we need to just create our own data, and project how monstrous Zen will be!

 

[DrMrLordX]

I'll pass, thanks.

 

[Dresdenboy]

Good that we live in a media environment full of money driven exagerations, so that poor humans can activate their archaic limbic systems for some excitations. It would be dull and sober otherwise.

40 new posts circling around a definition...

Must be like the Math conferences Thaleb wrote about.

BTW, Zen(+)/K12 cores can process 4 page table walks in parallel. SKL does 2.

 

[LTC8K6]

BTW, Zen(+)/K12 cores can process 4 page table walks in parallel. SKL does 2.

That doesn't necessarily mean that it will process 4 faster than SL will process 4, right?

 

[myocardia]

BTW, Zen(+)/K12 cores can process 4 page table walks in parallel. SKL does 2.

Makes sense to me, since it has double the cores & double the threads. BTW, have we heard anything at all official lately from AMD about K12? I keep only seeing them talk about Zen...but then, I'm not looking for news about K12, like I do about Zen, so I can see it having slipped by me.

 

[Dresdenboy]

Makes sense to me, since it has double the cores & double the threads. BTW, have we heard anything at all official lately from AMD about K12? I keep only seeing them talk about Zen...but then, I'm not looking for news about K12, like I do about Zen, so I can see it having slipped by me.

I think the PTWs are per core, but I'll recheck that.

K12 - nothing. Really seems to be on hold for Zen. Nevertheless as the archs share a lot, work done for Zen also helps K12's progress somewhat. And is the server world ready for an SMT ARM core, which is ~10% faster than Zen?
Src: David Kanter, who knows the differences between both uarchs.

 

[myocardia]

K12 - nothing. Really seems to be on hold for Zen. Nevertheless as the archs share a lot, work done for Zen also helps K12's progress somewhat. And is the server world ready for an SMT ARM core, which is ~10% faster than Zen?

Okay, that's what I was assuming, that it was unofficially on hold, at least for the time being.

I think the PTWs are per core, but I'll recheck that.

What is a PTW? I haven't heard that acronym before, I'm pretty sure.

 

[NostaSeronx]

What is a PTW?

Page table walks.

BTW, Zen(+)/K12 cores can process 4 page table walks in parallel. SKL does 2.

Which are pretty much irrelevant these days with Page Walk Caches in the MMU. PWCs allow for page table skipping.

 

[looncraz]

Page table walks.Which are pretty much irrelevant these days with Page Walk Caches in the MMU. PWCs allow for page table skipping.

They're most certainly not irrelevant as they are a longer running process critical for calculating a memory address not found in the TLB/PWC/MMU cache. Often the caches reduce how much of the table you need to walk rather than eliminating walks entirely, so being able to have twice as many walks in flight at once is still beneficial.

The page table is an in-memory tree, after-all, so a cache hit lets you jump over a level or two and get to a closer branch to the address translation you need with much fewer memory accesses.

Still, it's probably only worth up to about 10~15% extra performance for the applications which see frequent TLB misses (large databases and games, for example), but it could be much more useful for SMT. If AMD gives both threads equal resource access in their SMT implementation, this could be a very big enabler for SMT scaling.

 

[Tuna-Fish]

Page table walks.Which are pretty much irrelevant these days with Page Walk Caches in the MMU. PWCs allow for page table skipping.

The demand put on the MMU varies greatly depending on software -- a lot of well-behaved apps can live entirely out of tiny MMU caches, while other software can trash every level of every cache even if the caches are made huge. I've heard that large business apps written in Java or C# can spend a huge portion of their runtime in the page walker.

 

[Phynaz]

I think the PTWs are per core, but I'll recheck that.

Yes, they are.

 

[Phynaz]

ISCA presentation on page walks and TLB caches;

http://isca2010.inria.fr/media/slides/barr-ISCA10.pdf

Paper the presentation was developed from;

http://www.cs.rice.edu/CS/Architecture/docs/barr-isca10.pdf


Intel and AMD use different caching methods, each with their own strengths and weaknesses.

 

[mysticjbyrd]

They're most certainly not irrelevant as they are a longer running process critical for calculating a memory address not found in the TLB/PWC/MMU cache. Often the caches reduce how much of the table you need to walk rather than eliminating walks entirely, so being able to have twice as many walks in flight at once is still beneficial.

The page table is an in-memory tree, after-all, so a cache hit lets you jump over a level or two and get to a closer branch to the address translation you need with much fewer memory accesses.

Still, it's probably only worth up to about 10~15% extra performance for the applications which see frequent TLB misses (large databases and games, for example), but it could be much more useful for SMT. If AMD gives both threads equal resource access in their SMT implementation, this could be a very big enabler for SMT scaling.

If faster memory, higher frequency & tighter timings, is largely irrelevant in gaming with a good cpu, then why would this help games?

 

[Phynaz]

If faster memory, higher frequency & tighter timings, is largely irrelevant in gaming with a good cpu, then why would this help games?

Read what I posted. Depending upon application you can see a 50% performance increase, with 5% - 14% being typical.

Improve the TLB and get an entire generations' worth of performance improvement.

 

[looncraz]

If faster memory, higher frequency & tighter timings, is largely irrelevant in gaming with a good cpu, then why would this help games?

Memory timing (latency) effects games when the CPU is the bottleneck (which is increasingly less common, obviously). So, naturally, it is game dependent.

For most games, going from DDR3-1333 CL9 to DDR3-2133 CL9 will get you about 3~5% more FPS. Very tiny, to be sure.

However, the ability to double the in-flight page walks should have a bigger impact in the same scenarios as it is the lead-in latency for just being able to read the memory the program needs, so it more directly impacts performance, provided the memory can keep up with the requests. In games, it is quite common to have huge amounts of RAM allocated and to access many different addresses in close temporal proximity. Of course, the game core may run faster, but the game itself may run no faster due to some other bottleneck (such as lock contention, which is becoming an increasing issue with modern games).

 

[Dresdenboy]

ISCA presentation on page walks and TLB caches;

http://isca2010.inria.fr/media/slides/barr-ISCA10.pdf

Paper the presentation was developed from;

http://www.cs.rice.edu/CS/Architecture/docs/barr-isca10.pdf


Intel and AMD use different caching methods, each with their own strengths and weaknesses.

Thanks. That's interesting stuff! I'll check the patents for details regarding changes vs. the old AMD way.