Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

Vattila

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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

Untitled2.png


What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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BorisTheBlade82

BorisTheBlade82

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Timorous said:
Interesting.

Z4 CCD is 99M xtors per mm but if you exclude the IO and focus just on the cores and the cache the density is around 118M xtors per mm.

If Z4c is 16c with 32MB L3 cache and probably 2 of those IO blocks then it will need 10.8B (~4.15Bx2 for 16 cores + 2.35B for 32MB L3 + 0.7B*2 for the CCX IO) transistors which to fit in say a Z3 sized CCD would need a density of around 135M transistors per mm. Given we know the logic scales better than the cache on N5 and the fact that the cache amount is staying fixed and the core count is rising could AMD manufacture it on the current N5 node they already use? If 8c + 32MB L3 is 118M xtors per mm then it is logical to think 16c + 32MB L3 would be denser just due to the change in the ratio of logic to cache.
Click to expand...

It is very reasonable to assume, that they might make it happen (twice the cores on the same area. I also suspect them to use another IO - either full on SoIC or InFO-RDL.

Pure speculation:
I measured the block on the MI300 render that I suspect to be the 16c Zen4c CCD and it nicely fits the area bill (see the Zen5 thread around two weeks back, as ATM I am just too lazy).
 
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Tuna-Fish

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nicalandia said:
Likely just a misread
Click to expand...

What do you mean?

cpuz bench does two benchmarks. One for single-core, and another for all-core (or less, if you check the box that's not checked). Then it divides the all-core score with the single-core score, and reports that as the multi thread ratio. There is nothing to misread here.

The occam's razor option here is that someone doctored that screenshot, and raised either the single-core or the multi-core score.
 
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Hail The Brain Slug

Hail The Brain Slug

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Tuna-Fish said:
What do you mean?

cpuz bench does two benchmarks. One for single-core, and another for all-core (or less, if you check the box that's not checked). Then it divides the all-core score with the single-core score, and reports that as the multi thread ratio. There is nothing to misread here.

The occam's razor option here is that someone doctored that screenshot, and raised either the single-core or the multi-core score.
Click to expand...
???
It's expected the yield on a SMT processor is greater than the number of physical cores. The yield of 69 on a 64 core processor actually seems low, however due to the wide core count and power limits it probably has to clock down quite a bit for all core loads.

I don't see anything fishy about that number at all
 
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Hitman928

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Justinus said:
???
It's expected the yield on a SMT processor is greater than the number of physical cores. The yield of 69 on a 64 core processor actually seems low, however due to the wide core count and power limits it probably has to clock down quite a bit for all core loads.

I don't see anything fishy about that number at all
Click to expand...

That's not the problem. The problem is that the benchmark takes the multi threaded score and divides it by the single core score to get the multi threaded ratio. It doesn't care how many cores or threads there are or what frequency they are running at, it is just the ratio of the benchmark scores. In the screenshot, the shown multi threaded ratio doesn't match the actual ratio of the two scores. So in order to get a ratio that is different than the actual ratio of the two scores, someone would have had to Photoshop at least one of the scores and didn't know (or forgot) to edit the multi threaded ratio as well to cover their tracks.
 
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Hail The Brain Slug

Hail The Brain Slug

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Hitman928 said:
That's not the problem. The problem is that the benchmark takes the multi threaded score and divides it by the single core score to get the multi threaded ratio. It doesn't care how many cores or threads there are or what frequency they are running at, it is just the ratio of the benchmark scores. In the screenshot, the shown multi threaded ratio doesn't match the actual ratio of the two scores. So in order to get a ratio that is different than the actual ratio of the two scores, someone would have had to Photoshop at least one of the scores and didn't know (or forgot) to edit the multi threaded ratio as well to cover their tracks.
Click to expand...

Lol guess I should have done my own math
 
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Tuna-Fish

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nicalandia said:
You are reading too much on this, its clearly a CPUZ Misread on the multiplier thats all. Its not the first time CPUZ misreads Genoa.
Click to expand...

THERE IS NO INFORMATION BEING READ FROM ANYWHERE. Again: The CPU-z benchmark does two tests, a multi-core test and a single core test. Then it reports both of those scores, and also divides the multicore score with the single-core score, and reports that as the multi thread ratio. Both of those numbers come from CPUz itself. Then it does the math of doing the division itself. There is absolutely no avenue here for this to be an error, or to be a honest mistake. This screenshot has felt the gentle caress of photoshop.
 
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nicalandia

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Tuna-Fish said:
THERE IS NO INFORMATION BEING READ FROM ANYWHERE.
Click to expand...
That old version of CPUZ(2.01) does not have support for Genoa, a few things are not display succesful.
Screenshot_20230313-201217_Chrome.jpg


When I said misread I ment the multiplier number(66.03) not being displayed correctly as are other componentes on the CPU. Not that the MT score is incorrect

Screenshot_20230313-195922_Chrome.jpg

That's The 9654 by the way..

Screenshot_20230313-200837_Chrome.jpg


I have my sources in China(sellers, technicians) Trying to get MT performance on Bergamo as we speak.
 
BorisTheBlade82

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Tuna-Fish

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nicalandia said:
That old version of CPUZ(2.01) does not have support for Genoa, a few things are not display succesful.

When I said misread I ment the multiplier number(66.03) not being displayed correctly as are other componentes on the CPU. Not that the MT score is incorrect
Click to expand...

Again, this does not matter. Even if the CPU is completely unsupported, the MT/ST ratio is not read from the CPU.

When you hit the button called "bench", the program does a sequence of steps.
1. Run a multi-threaded benchmark. Record the result, and display it as the MT score.
2. Run a single-threaded benchmark. Record the result, and display it as the ST score.
3. Compute MT score/ ST score, and display that as the multi threaded ratio. Again, this number is not read from anywhere. It doesn't matter that CPU-Z doesn't support that CPU. All it is is MT_SCORE/ST_SCORE. If it is not that, the only reason is that something got tampered with.
nicalandia said:
I have my sources in China(sellers, technicians) Trying to get MT performance on Bergamo as we speak.
Click to expand...

If that screenshot was from your sources, your sources were just lying to you.
 
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nicalandia

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Tuna-Fish said:
If that screenshot was from your sources, your sources were just lying to you.
Click to expand...
I trust my sources, who is going to the trouble to photoshop an image to fake CPUZ numbers that hardly anyone care about? The CPUs are real, the performance is real, they make a living selling ES and QS sample CPUs. But I respect your input.

On a different subject. AMD Just launched Genoa embeded, Does this means Siena is cancelled?

AMD Launches The EPYC Embedded 9004 Series - Phoronix

www.phoronix.com www.phoronix.com
 
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Tuna-Fish

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oldcpuz.png
Just to make the point, I downloaded a random old CPU-Z version from 2016, which certainly does not support or know about my CPU, and ran the benchmark. The result is redactedbecause I have tons of stuff running in the background, but the ratio is exactly what it's supposed to be.



Profanity in tech is not allowed


esquared
Anandtech Forum Director
 
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nicalandia

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Tuna-Fish said:
Why? That screenshot was clearly faked. Either you are trying to fool us yourself, or you got taken for a ride. Why can't you just accept that the screenshot was faked and move on?
Click to expand...
I really don't care eitherway, These people have the real hardware, I am basically having to "becoming friends" with Hentai Loving Grown men that dress like girls on their free time so I can get access to screenshots every now and then.
 
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Tuna-Fish

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nicalandia said:
I really don't care eitherway, These people have the real hardware, I am basically having to "becoming friends" with Hentai Loving Grown men that dress like girls on their free time so I can get access to screenshots every now and then.
Click to expand...

They might have the real hardware, they are still editing the screenshots they post.
 
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nicalandia

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Let's talk about Siena... Has AMD cancelled them?

This is from Phoronix: "AMD is using Embedded World 2023 in Nürnberg to launch the EPYC Embedded 9004 series as their 4th Gen EPYC processors intended for telecommunications, edge computing, automation, and IoT applications. "
 
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Joe NYC

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Timorous said:
Interesting.

Z4 CCD is 99M xtors per mm but if you exclude the IO and focus just on the cores and the cache the density is around 118M xtors per mm.

If Z4c is 16c with 32MB L3 cache and probably 2 of those IO blocks then it will need 10.8B (~4.15Bx2 for 16 cores + 2.35B for 32MB L3 + 0.7B*2 for the CCX IO) transistors which to fit in say a Z3 sized CCD would need a density of around 135M transistors per mm. Given we know the logic scales better than the cache on N5 and the fact that the cache amount is staying fixed and the core count is rising could AMD manufacture it on the current N5 node they already use? If 8c + 32MB L3 is 118M xtors per mm then it is logical to think 16c + 32MB L3 would be denser just due to the change in the ratio of logic to cache.
Click to expand...

Good points, it all makes sense.

One thing that was surprising was the total number of transistors in the V-Cache.
 
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