Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Hougy]

https://twitter.com/x/status/1427547398121746432

Zen4 die size

 

[coercitiv]

Looks like power goes up for AMD as well. Liquid cooling the new norm, lol?

Wow, take a look at Tcase requirements for 170W TDP.

 

[uzzi38]

https://twitter.com/x/status/1427547398121746432

Zen4 die size

Yeah, ExecutableFix leaked that sort of information a while ago. Die sizes remaining the same with Zen 4.

Safe to assume Zen 4 comes with enough changes to the core to keep per-core sizes rather similar, despite the hefty node shrink.

 

[Abwx]

Compilation of those alleged leaks :

Genoa mit Zen 4: Umfangreiche Details zu AMDs nächster Server-CPU

Ein Support-Dokument für AMDs nächsten Server-Sockel SP5 gibt auch Details zu Zen 4 preis: 12 CPU-Dies inklusive AVX-512 gibt es für Genoa.

www.computerbase.de

 

[DisEnchantment]

Zen4 seems to belong to the same Family 19H like Zen3. Core uArch and ISA (Zen 3 added a whole bunch of extensions to the ISA over Zen2 though) would largely remain similar.

I wonder where the major part of the perf will come from.
AVX512 is confirmed. Pretty clear when AMD never objected to using feature level 4 in gcc/clang for x86 being AVX512 mandatory.
Interposer will have to wait for a bit.

 

[Joe NYC]

2 different die heights of the package have a difference of 0.5mm, which can accommodate 10 layers of stacking or 8 + some overhead.

 

[stebler]

Is this old news?

 

[Joe NYC]

Zen4 seems to belong to the same Family 19H like Zen3. Core uArch and ISA (Zen 3 added a whole bunch of extensions to the ISA over Zen2 though) would largely remain similar.

I wonder where the major part of the perf will come from.
AVX512 is confirmed. Pretty clear when AMD never objected to using feature level 4 in gcc/clang for x86 being AVX512 mandatory.
Interposer will have to wait for a bit.

Almost no die size savings gong from GloFo 12nm to 6nm TSMC.
424mm2 vs 397mm2

But a lot of room to stack something on top of this die

 

[leoneazzurro]

Almost no die size savings gong from GloFo 12nm to 6nm TSMC.
424mm2 vs 397mm2

But a lot of room to stack something on top of this die

Well it seems the I/O die will use 12 channels of DDR5 RAM while the older one was using 8 channels of DDR4. Moreover it should have more IF links. I think the space needed to accomodate all these connection alone will be a big part of the die size.

 

[Joe NYC]

Well it seems the I/O die will use 12 channels of DDR5 RAM while the older one was using 8 channels of DDR4. Moreover it should have more IF links. I think the space needed to accomodate all these connection alone will be a big part of the die size.

Perhaps the bumps alone needed to accommodate these dictate the minimum die size.

 

[DrMrLordX]

I wonder where the major part of the perf will come from.

Moving from N7 (w/secret sauce!) to N5 will bring with it some performance improvement @ isopower. Not sure if that will be the only improvement, but it will count for something. I doubt it'll be +29% though.

 

[eek2121]

Moving from N7 (w/secret sauce!) to N5 will bring with it some performance improvement @ isopower. Not sure if that will be the only improvement, but it will count for something. I doubt it'll be +29% though.

I can guarantee it’ll be at least 50% faster.

…

It has 50% more cores! 🤣

In all seriousness, I think you are downplaying the dramatic part that DDR5 will play. 12 channels of DDR5 drastically increases the amount of memory bandwidth available. Previous generations can be bandwidth starved in certain scenarios.

AVX-512 is going to play a considerable part as well. I imagine the chip likely has new AVX units.

The TDP has also jumped, though there is the question of whether that is only due to the core count increase or a frequency increase as well.

29% sounds a bit conservative if you ask me.

 

[Joe NYC]

In all seriousness, I think you are downplaying the dramatic part that DDR5 will play. 12 channels of DDR5 drastically increases the amount of memory bandwidth available. Previous generations can be bandwidth starved in certain scenarios.

The problem is that, unless there was a major improvement in Infinity Fabric, each CCD is limited to 2 DDR4 channels worth of bandwidth down and 1 channel up.

So one CCD, or 1 core within it can never get at all the bandwidth - unless the interconnect is majorly upgraded.

 

[coercitiv]

29% sounds a bit conservative if you ask me.

@DrMrLordX was talking about performance per clock.

 

[eek2121]

The problem is that, unless there was a major improvement in Infinity Fabric, each CCD is limited to 2 DDR4 channels worth of bandwidth down and 1 channel up.

So one CCD, or 1 core within it can never get at all the bandwidth - unless the interconnect is majorly upgraded.

Given it is a brand new IO die, that basically guarantees there is a new version of IF.

 

[Joe NYC]

Given it is a brand new IO die, that basically guarantees there is a new version of IF.

Yes, also Infinity Architecture 3 was announced.

But the interconnect, even if it was improved proportionally by ratio of DDR5 vs. DDR4 bandwidth is on its last legs.

 

[uzzi38]

Is this old news?

Not old, definitely new.

Also, these appear to be peak numbers. Peak power draw figures for Milan IOD in the same documents is about the same which is a surprise. Highest is 114W.

 

[Mopetar]

Almost no die size savings gong from GloFo 12nm to 6nm TSMC.
424mm2 vs 397mm2

But a lot of room to stack something on top of this die

Has it been confirmed they're going to TSMC for the IO die anywhere? It's just as likely they're using the updated 12nm Global Foundries node that has better power characteristics. There was certainly room in the old IO for a more compact design. Maybe not quite as much if they're adding more overall IO, but if it weren't otherwise changed I'd make a strong bet on it not being TSMC given the size.

Either way the lack of size reduction isn't surprising. I don't know how many posts I made trying to tell people that IO doesn't benefit from node shrinks, but I think that there's no real denying it at this point unless you don't believe the leaks.

 

[eek2121]

Has it been confirmed they're going to TSMC for the IO die anywhere? It's just as likely they're using the updated 12nm Global Foundries node that has better power characteristics. There was certainly room in the old IO for a more compact design. Maybe not quite as much if they're adding more overall IO, but if it weren't otherwise changed I'd make a strong bet on it not being TSMC given the size.

Either way the lack of size reduction isn't surprising. I don't know how many posts I made trying to tell people that IO doesn't benefit from node shrinks, but I think that there's no real denying it at this point unless you don't believe the leaks.

I don’t believe so, but it is definitely on a smaller process.

 

[Mopetar]

I don’t believe so, but it is definitely on a smaller process.

Still could be Global Foundries 12LP+ which had a 15% area reduction over the old 12LP node that AMD used previously.

The only other good explanations I've heard for AMD commuting to buy as many wafers as they did is a new Athlon line on that node or the possibility of them using it for massive amounts of HBM2. The first seems more likely, but would constitute such a massive number of chips that I find it hard to believe that would be the only use.

 

[Ajay]

View attachment 48867

Looks like power goes up for AMD as well. Liquid cooling the new norm, lol?

More cores, the war is approaching. 12/24 the new mainstream. Can’t wait, the future is bright 😈

The '170' is suspicious. It is not listed as 170W - so we don’t know the actual power output, could be unobtainium units

 

[Ajay]

Is this old news?

Pfft, read the table incorrectly.

 

[coercitiv]

The '170' is suspicious. It is not listed as 170W - so we don’t know the actual power output, could be unobtainium units

Not suspicious at all, it's Watts. Even with the typo the data is clear, since we have all the variables required for TDP calculation right there in the table:

ADM TDP forumla is as follows:
TDP (Watts) = (tCase°C - tAmbient°C)/(HSF θca)
where HSF θca (°C/W) is defined as the minimum °C per Watt rating of the heatsink to achieve rated performance

and the numbers fit
169.56=(46.7-35)/0.069

The problem here is tCase is very low, and one doesn't chose a much lower die/heatspreader junction temperature unless it is actually needed. I reckon 170W TDP SKU(s) will have very agressive boosting, probably the highest in the entire lineup.

 

[Ajay]

Not suspicious at all, it's Watts. Even with the typo the data is clear, since we have all the variables required for TDP calculation right there in the table:

ADM TDP forumla is as follows:
TDP (Watts) = (tCase°C - tAmbient°C)/(HSF θca)
where HSF θca (°C/W) is defined as the minimum °C per Watt rating of the heatsink to achieve rated performance

and the numbers fit
169.56=(46.7-35)/0.069

The problem here is tCase is very low, and one doesn't chose a much lower die/heatspreader junction temperature unless it is actually needed. I reckon 170W TDP SKU(s) will have very agressive boosting, probably the highest in the entire lineup.

Uhm, the emoji was, I thought, a clear indication that my post was sarcasm.

 

[Magic Carpet]

The problem here is tCase is very low

I wonder how easy it’s going to keep it cool. I remember, Thuban had also a low tCase (62) relatively speaking, but it ran quite cool even with stock cooling at stock clocks. But 46 is even lower than that, the die size must be big enough to remove heat effectively.