Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[jamescox]

If you listen to Lisa Su, she states that her goal for AMD is to be leader of the HPC.

She achieved in in servers (gaming as a side bonus). She is not about to relinquish it because some on this thread think that stacking 2nd $6 die of silicon is just too much trouble over stacking the first one.

It isn’t about “how much trouble” it is. A lot of things in the industry have to be decided sometimes months if not years ahead of time. It might be that the process makes it easy to stack a different number of die and it might be that number of die is something that was decided a long time ago and is not easily changeable now. I don’t know how much trouble it is to adjust for different heights. I suspect that they will attempt to keep the height the same such that the stacked die and non-stacked die are interchangeable, so 1, 2, and 4 would all have to be polished down by different amounts. I still doubt that they will have a separate 2 layer part. I don’t know how much trouble it would be to manufacture, but if they can’t win with 192 MB 5950X3D (2 CCD x 96 MB per CCD) then I don’t know if a 320 MB (2 CCD x 160 MB per CCD) cpu will do it either.

Nvidia has been good at predicting what will be important or just making what they implemented seem important. It wasn’t that long ago that upscaling was thought of as a bad thing. It was only implementations that couldn’t render it natively that would resort to the kludge of upscaling. Now, some fancy AI upscaler is suddenly a must have feature and not being able to render it natively is somehow fine.

All of the major manufactures have been hit with issues where decisions made moths or years ago did not turn out to be the best choices. They have to make decisions on a lot of features years in advance, so if they guess right, they look really good. Guessing wrong can be a disaster though. Intel seems to have thought that they could use monolithic die up until they move to die stacking which is why they have no completion to most Epyc parts right now. How quickly could intel have fixed that? If thier process tech was yielding fine, it still would have taken a few years to shift to MCM or stacked designs.

We don’t really know that much about TSMC’s SoIC stacking, but I am still thinking that only single layer will be making it to consumers level parts. It would be interesting to see whether game performance still scales with larger cache parts. I think the 4 high stack Milan-X3D will be showing up a bit later than the single layer stacked parts anyway.

 

[Joe NYC]

It isn’t about “how much trouble” it is. A lot of things in the industry have to be decided sometimes months if not years ahead of time.

Some things about Zen 3 were planned years ago, including that it will have 3D capability.

Other things - fine tuning it - are quite new. First rumors of B2 stepping of Zen 3 main chiplet just came out late early May, IIRC, saying that it will just improve manufacturability.

Not much attention was paid to it, and the news sort of disappeared from view, and then AMD hit us with Zen 3D announcement. And not many people are connecting the dots here. That B2 stepping is improving manufacturability options of 3D stacking as well.

Another thing to keep in mind: This one Zen 3 die will be making close to $2 billion per quarter for AMD in revenue. It only makes sense that AMD has optimized the hell out of it and covered most of the possibilities.

It might be that the process makes it easy to stack a different number of die and it might be that number of die is something that was decided a long time ago and is not easily changeable now. I don’t know how much trouble it is to adjust for different heights. I suspect that they will attempt to keep the height the same such that the stacked die and non-stacked die are interchangeable, so 1, 2, and 4 would all have to be polished down by different amounts.

In my non-expert opinion, these are trivial issues to solve. The layers of L3 are extremely thin, thinner than most people imagine.

And thinning the base die may be the last step before stacking L3.

But this is precisely what I had in mind when I posted the comment. Lisa Su has a goal for for AMD to be the leader in High Performance Computing.

Can you imagine an employee coming back to her saying: "Sorry, we can't be the leader of High Performance computing because we have trouble figuring out different heights we will need for different levels of stacking."

I still doubt that they will have a separate 2 layer part. I don’t know how much trouble it would be to manufacture, but if they can’t win with 192 MB 5950X3D (2 CCD x 96 MB per CCD) then I don’t know if a 320 MB (2 CCD x 160 MB per CCD) cpu will do it either.

I don't think AMD needs to segment itself to death with different levels of stacking. AMD just needs one that wins the gaming (at worst ties ADL), and one that has Milan X competing well with Sapphire Rapids

All of the major manufactures have been hit with issues where decisions made moths or years ago did not turn out to be the best choices. They have to make decisions on a lot of features years in advance, so if they guess right, they look really good. Guessing wrong can be a disaster though. Intel seems to have thought that they could use monolithic die up until they move to die stacking which is why they have no completion to most Epyc parts right now. How quickly could intel have fixed that? If thier process tech was yielding fine, it still would have taken a few years to shift to MCM or stacked designs.

AMD hit the home run with chiplets and with stacking. Which is why I don't think the tiny challenges (in comparison), like how many layers, are going to trip up AMD.

We don’t really know that much about TSMC’s SoIC stacking, but I am still thinking that only single layer will be making it to consumers level parts. It would be interesting to see whether game performance still scales with larger cache parts. I think the 4 high stack Milan-X3D will be showing up a bit later than the single layer stacked parts anyway.

Like I said in the previous post, if 1 level of L3 is good enough to just narrowly lose the performance crown to ADL, there is no point in releasing it.

AMD has several cards to play, and a lot of time to decide which card to play.

So when you say single layer for consumer parts, is like Lisa making the decision now, without knowing where ADL is, and going on a 6 month sailing vacation around the world.

More likely, AMD will watch for ADL performance leaks and info and will make the decision (late) based on that. Will play the card best for the scenario at hand.

With Milan X, that one will most likely be based on best long term strategy than short term gamesmanship. For that, I think AMD needs to have a way to validate for all possible L3 scenarios, so that going forward, AMD can sell any semi-custom configuration customers (with deep pockets) ask for.

 

[JoeRambo]

Like I said in the previous post, if 1 level of L3 is good enough to just narrowly lose the performance crown to ADL, there is no point in releasing it.

The diminishing points of L3 start to kick in soon. And it helps more in workloads like games, and does not work in say Cinebench where workloads fit L2.
At some point secondary effects like bandwidth, having limited TLB coverage ( even if TLB walks would get massive help from page tables being in L3 cache) start to limit full potential of such large caches.
THO i have to admit that with hindsight AMD overbuilt their cores in this department, i mean each core has 6 page table walkers and 64 L2->L3 miss queue means they have planned for huge L3 from the start. Zero chance to have 6 outstanding TLB misses that walk memory, while L3 would serve them fast enough to make sense.

So frankly i see AMD coming with 1 layer only on consumer desktop. 96MB of L3 is plenty to compete with 30MB of L2 Intel will have on Alderlake. And if Alderlake is as strong core as Cinebench results suggest - it will still have its wins, but not in gaming and not in coveted gaming minimum FPS.

 

[Joe NYC]

The diminishing points of L3 start to kick in soon. And it helps more in workloads like games, and does not work in say Cinebench where workloads fit L2.
At some point secondary effects like bandwidth, having limited TLB coverage ( even if TLB walks would get massive help from page tables being in L3 cache) start to limit full potential of such large caches.
THO i have to admit that with hindsight AMD overbuilt their cores in this department, i mean each core has 6 page table walkers and 64 L2->L3 miss queue means they have planned for huge L3 from the start. Zero chance to have 6 outstanding TLB misses that walk memory, while L3 would serve them fast enough to make sense.

So frankly i see AMD coming with 1 layer only on consumer desktop. 96MB of L3 is plenty to compete with 30MB of L2 Intel will have on Alderlake. And if Alderlake is as strong core as Cinebench results suggest - it will still have its wins, but not in gaming and not in coveted gaming minimum FPS.

Good points. But I don't think 96MB Zen 3D would have the gaming crown in the bag.

I would like to see AMD be prepared to release a maxed out gaming CPU, a 5 GHz boost clock 68x0X (6840X) with 4 layers. for a big win with optional 6800x and 6810x with 0 and 1 levels.

Then, AMD would be selling affordable DDR4 platform, while Intel has to scramble with expensive DDR5 platform just to barely keep up. Good situation to be in for AMD.

Also, if Zen 3D can secure the gaming CPU win with N7(N6?) process node, AMD can concentrate their energies and precious N5 capacity in 2022 elsewhere: Genoa, RDNA3.

 

[jamescox]

Some things about Zen 3 were planned years ago, including that it will have 3D capability.

Other things - fine tuning it - are quite new. First rumors of B2 stepping of Zen 3 main chiplet just came out late early May, IIRC, saying that it will just improve manufacturability.

Not much attention was paid to it, and the news sort of disappeared from view, and then AMD hit us with Zen 3D announcement. And not many people are connecting the dots here. That B2 stepping is improving manufacturability options of 3D stacking as well.

Another thing to keep in mind: This one Zen 3 die will be making close to $2 billion per quarter for AMD in revenue. It only makes sense that AMD has optimized the hell out of it and covered most of the possibilities.



In my non-expert opinion, these are trivial issues to solve. The layers of L3 are extremely thin, thinner than most people imagine.

And thinning the base die may be the last step before stacking L3.

But this is precisely what I had in mind when I posted the comment. Lisa Su has a goal for for AMD to be the leader in High Performance Computing.

Can you imagine an employee coming back to her saying: "Sorry, we can't be the leader of High Performance computing because we have trouble figuring out different heights we will need for different levels of stacking."



I don't think AMD needs to segment itself to death with different levels of stacking. AMD just needs one that wins the gaming (at worst ties ADL), and one that has Milan X competing well with Sapphire Rapids



AMD hit the home run with chiplets and with stacking. Which is why I don't think the tiny challenges (in comparison), like how many layers, are going to trip up AMD.



Like I said in the previous post, if 1 level of L3 is good enough to just narrowly lose the performance crown to ADL, there is no point in releasing it.

AMD has several cards to play, and a lot of time to decide which card to play.

So when you say single layer for consumer parts, is like Lisa making the decision now, without knowing where ADL is, and going on a 6 month sailing vacation around the world.

More likely, AMD will watch for ADL performance leaks and info and will make the decision (late) based on that. Will play the card best for the scenario at hand.

With Milan X, that one will most likely be based on best long term strategy than short term gamesmanship. For that, I think AMD needs to have a way to validate for all possible L3 scenarios, so that going forward, AMD can sell any semi-custom configuration customers (with deep pockets) ask for.

being a leader in HPC is almost a given at this point due to supporting 4 layers; possibly up to 288 MB per cpu die, possibly 2304 MB in one Epyc package. This has nothing to do with whether we are going to get 4 layer stacks in consumer Ryzen parts. Every different model you add changes the process. You don’t want to be building a huge number of variants. The 4 stack chips are inherently more risky. There is a lot more chances of something going wrong and ending up with a defective part. That means they charge more for them. Have you looked at how much the large cache F-series Epycs cost? They do still have an 8 core Milan, but it is 8 separate CCDs. That is a lot of silicon.

Regardless of the manufacturing, I don’t think games will continue to scale with hundreds of MB of L3. That is my main reason for not expecting it in the consumer market. It will be interesting if the 2+ GB Milan exists and someone runs some games on it. They also don’t want to take sales away from more expensive parts. AMD doesn’t segment the market in the same ways as Intel, but if I could get Ryzen cpu with 4 layers of cache die, I would have no reason to get a bigger machine for a development workstation. That large of cache will accelerate compile jobs by a massive amount.

 

[Ajay]

Good points. But I don't think 96MB Zen 3D would have the gaming crown in the bag.

I would like to see AMD be prepared to release a maxed out gaming CPU, a 5 GHz boost clock 68x0X (6840X) with 4 layers. for a big win with optional 6800x and 6810x with 0 and 1 levels.

No, it's just not going to happen. It doesn't make economic sense - more silicon - more complex packaging. It doesn't make sense relative to likely packaging defect rates. It just doesn't make sense. What use would it be to AMD to make a 5900/5950X + V-Cache that goes for $1200+ $$$? Just to pip Intel by 10 FPS? I really don't get this line of thinking.

 

[DisEnchantment]

5th Gen CoWoS-S Extends 3 Reticle Size

[Subscriber Content] TSMC's 5th Generation CoWoS-S Extends 3 Reticle Size.

fuse.wikichip.org

TSMC introduces 3x reticle sized interposers. 2600mm2 , CoWoS-S5
Article needs subscription.
Using ExecuFix scaled mockup, the new interposer will cover the external perimeter shown below compared to the last gen interposer with the inner perimeter shown.
Possibilities...

 

[eek2121]

No, it's just not going to happen. It doesn't make economic sense - more silicon - more complex packaging. It doesn't make sense relative to likely packaging defect rates. It just doesn't make sense. What use would it be to AMD to make a 5900/5950X + V-Cache that goes for $1200+ $$$? Just to pip Intel by 10 FPS? I really don't get this line of thinking.

I don't think you realize how much money AMD makes from the 5950x, or from gamers for that matter. People keep going on about how "gamers don't matter" or are a "side business" or "happen to benefit", but gamers saved AMD from bankruptcy, and enthusiast chips represent a significant amount of revenue for AMD (or Intel for that matter). If enthusiasts stop buying chips from AMD overnight, AMD would be in dire straights. The last I checked gaming was a nearly 200 billion dollar industry, and AMD is eyeballs deep in it. A 5950x likely costs AMD under $200 to make. The margins on that chip alone allow them to sacrifice margins in other areas.

Do I expect AMD to go nuts with the v-cache? I won't speculate on that. It depends on the market (read: Alder Lake) and the performance benefit for larger cache sizes.

That being said, my 5950x works just fine, so I won't be upgrading for a while, regardless (even though I would LOVE to have an excuse to buy one )

 

[LightningZ71]

It seems to me that having AM4 chips with a large V-Cache (be it 1 stack or four) is still more of a hedge against Intel's DDR5 platform AlderLake products. That higher bandwidth and lower effective latency will be hard to counter in many applications without having a gigantic L3 cache to keep data close to the cores. Having 12-16MB of L3 per core in multi-threaded scenarios is nothing to sneeze at.

 

[Ajay]

A 5950x likely costs AMD under $200 to make. The margins on that chip alone allow them to sacrifice margins in other areas.

Plus operating expenses, advertising, taxes, re-distributor and retailer's cut...etc. Also, they don't 'sacrifice' margins in other areas - that would be stupid (recall Intel's efforts at getting in to mobile devices).

 

[Saylick]

It seems to me that having AM4 chips with a large V-Cache (be it 1 stack or four) is still more of a hedge against Intel's DDR5 platform AlderLake products. That higher bandwidth and lower effective latency will be hard to counter in many applications without having a gigantic L3 cache to keep data close to the cores. Having 12-16MB of L3 per core in multi-threaded scenarios is nothing to sneeze at.

Absolutely it is. As many have mentioned, AM4 + Zen 3 + Vcache + DDR4 is a solid mature platform for those who don't want to spend extra on the latest and greatest while offering competitive performance. AM5 + Zen 4 + DDR5 would be the premium option for those who want the cutting edge and that extra oomph.

It's almost like Vcache is the CPU version of the design philosophy behind RDNA2, where instead of going with a wider memory bus and newer memory standard, they slapped on even more cache.

 

[Mopetar]

Halo products are important as much for mindshare as for the additional money they make. People actually talk about AMD being the best right now, not just an alternative that's almost as good for a fraction of the price.

Also high margin products don't need to sell in high numbers to make them worthwhile. If you were to assume that a new Zen 3 CPU cost AMD $200 on average after including fixed costs, etc. then they need to sell 4x as many $300 CPUs as they do $600 CPUs to generate the same profit. As the sale price gets closer to that $200 cost the numbers get even more distorted.

 

[A///]

Then, the move of IO die to TSMC make these chiplets "eligible" for integrating additional TSMC technology, including packaging and stacking technologies.

Yep. Precisely what I realized when I was first told that in passing. Time will tell. I ended up getting a 10700K build up and running many months ago. I've gone back to work for a while and barely use my computer as is. May end up getting Zen 4 when it matures.

 

[Joe NYC]

No, it's just not going to happen. It doesn't make economic sense - more silicon - more complex packaging. It doesn't make sense relative to likely packaging defect rates. It just doesn't make sense. What use would it be to AMD to make a 5900/5950X + V-Cache that goes for $1200+ $$$? Just to pip Intel by 10 FPS? I really don't get this line of thinking.

Zen 3D version of single chiplet CPU with V-Cache, which I called 6800x, even with 4 layers of S3 V-Cache is most likely cheaper than 5950x with 2 CCDs.

AMD released a $799 5950x just to beat Intel in Cinebench. Why do you think it wouldn't make sense to release 6800x with > 1 layer of L3, in order to keep the gaming crown?

it seems to me that the gaming market is bigger than market of people who run Cinebench benchmark. (or other highly multithreaded apps where 8 cores runs out of steam).

 

[Joe NYC]

5th Gen CoWoS-S Extends 3 Reticle Size

[Subscriber Content] TSMC's 5th Generation CoWoS-S Extends 3 Reticle Size.

fuse.wikichip.org

TSMC introduces 3x reticle sized interposers. 2600mm2 , CoWoS-S5
Article needs subscription.
Using ExecuFix scaled mockup, the new interposer will cover the external perimeter shown below compared to the last gen interposer with the inner perimeter shown.
Possibilities...

View attachment 48236

The I/O die for Genoa will likely be quite a bit smaller.

But I don't think this is the right long term direction to take for AMD, with all sorts of stacking becoming possible, possibly spanning chiplet to chiplet, and hybrid bond being a superior to micro-bumps.

 

[Ajay]

Zen 3D version of single chiplet CPU with V-Cache, which I called 6800x, even with 4 layers of S3 V-Cache is most likely cheaper than 5950x with 2 CCDs.

AMD released a $799 5950x just to beat Intel in Cinebench. Why do you think it wouldn't make sense to release 6800x with > 1 layer of L3, in order to keep the gaming crown?

it seems to me that the gaming market is bigger than market of people who run Cinebench benchmark. (or other highly multithreaded apps where 8 cores runs out of steam).

AMD didn't release the 5950X just to beat Intel in Cinebench. 1 layer of L3 makes total sense, just not 4. As someone else posted here, diminishing returns for increasing failure rates in packaging (for consumer CPUs).

 

[Joe NYC]

AMD didn't release the 5950X just to beat Intel in Cinebench. 1 layer of L3 makes total sense, just not 4. As someone else posted here, diminishing returns for increasing failure rates in packaging (for consumer CPUs).

Most of the performance enhancing elements have diminishing returns. 2nd core has diminishing returns over 1st core.

9th through 16th core of 5950X add just about zero in most applications. The returns of adding the entire CCD to the CPU diminished to zero in vast number of apps. But AMD launched, and gained a lot of performance in a tiny subset of apps.

Why do you think the logic would change for V-Cache? Why would AMD go all out with 5950X to chase one small niche, but not do the same with V-Cache for a much larger segment - gaming?

All, while the V-Cache is cheaper than 2nd CCD, and the competition AMD is facing (in Alder Lake) is far stronger than before, loss of performance leadership is quite real?

 

[Vattila]

1 layer of L3 makes total sense, just not 4.

We'll just have to wait and see. There are so many variables here. Also, there is the fact that these are chiplets usable across mainstream desktop, HEDT/workstation and server. Assuming they stack known-good-die, and the V-Cache stacking has little chance of ruining the good CCD, then nearly all of the output from the stacking process should be usable CCDs, no matter the yield of the stacking itself.

For argument sake, say the stacking yield is low (i.e. TSV failures), so AMD needs to run high 4-stack volume to get enough CCDs with all V-Cache layers fully functional to satisfy their top SKU requirements in the server space. That would leave a high volume of salvaged CCDs with 3 or less layers functional. E.g. say 60% of the CCDs have no functional layers, 40% have 1 or more layers functional, 20% have 2 or more layers functional, 10% have 3 or more layers functional, and just 5% have all 4 layers functional.

 

[DisEnchantment]

We'll just have to wait and see. There are so many variables here. Also, there is the fact that these are chiplets usable across mainstream desktop, HEDT/workstation and server. Assuming they stack known-good-die, and the V-Cache stacking has little chance of ruining the good CCD, then nearly all of the output from the stacking process should be usable CCDs, no matter the yield of the stacking itself.

For argument sake, say the stacking yield is low (i.e. TSV failures), so AMD needs to run high 4-stack volume to get enough CCDs with all V-Cache layers fully functional to satisfy their top SKU requirements in the server space. That would leave a high volume of salvaged CCDs with 3 or less layers functional. E.g. say 60% of the CCDs have no functional layers, 40% have 1 or more layers functional, 20% have 2 or more layers functional, 10% have 3 or more layers functional, and just 5% have all 4 layers functional.

4 stacks of 36mm2 KGSD = 144mm2 per CCD + 80mm2. 468mm2 of N7 die area for a 5950X with 4-Hi KGSD V Cache, add to that a complex packaging.
AMD is selling 160mm2 of N7+cIOD for 800USD.
They need 3x more die area per CCD. Chances are very low. There are simply not enough wafers for this.

 

[Joe NYC]

4 stacks of 36mm2 KGSD = 144mm2 per CCD + 80mm2. 468mm2 of N7 die area for a 5950X with 4-Hi KGSD V Cache, add to that a complex packaging.

I am advocating an alternative high end CPU for ST. Max out clock speed and V-Cache and dump 2nd CCD to beat Alder Lake in gaming.

AMD already has a high end CPU for MT in 5950X. Gamers are not super interested in this one.

Cost of 4x 36mm2 = 144mm2 of SRAM is probably less than 1 logic CCD of 80mm2.

My completely wild guess:
1 Logic Wafer = 2 SRAM Wafers

AMD is selling 160mm2 of N7+cIOD for 800USD.
They need 3x more die area per CCD. Chances are very low. There are simply not enough wafers for this.

AMD is already selling this CPU for $800 5950X CPU that buys nothing for gamers over 5800x, wastes a CCD, wastes half of the power envelope, wastes 2 highest binning parts on it.

 

[Vattila]

I am advocating an alternative high end CPU for ST.

Rather than aim for multi-layer V-Cache in the mainstream, which may be difficult to do due to cost and sparse capacity, perhaps we'll see the gaming crown move to HEDT. I guess AMD would love to say that their upcoming Threadrippers make no compromises — with lots of "Zen 3" cores, high clock speed, huge memory bandwidth, and copious amounts of cache.

I've aired that idea before:

Speculation: PC enthusiasts will migrate to HEDT

With the latest rumour that EPYC 2 will use eight 8-core dies, it seems likely that the upcoming Ryzen 3000 series will be using one of those dies, and that we'll still have a maximum of 8 cores in the mainstream desktop segment next year. Perhaps 8 cores on the mainstream platform will remain...

forums.anandtech.com

 

[Ajay]

Most of the performance enhancing elements have diminishing returns. 2nd core has diminishing returns over 1st core.

Uh, no. More and more software uses more than one core. The gains are not diminished much, or at all, for well designed software.

Why do you think the logic would change for V-Cache? Why would AMD go all out with 5950X to chase one small niche, but not do the same with V-Cache for a much larger segment - gaming?

They ARE adding V-Cache for gamers, but it's a cutting edge technology. These will be their first CPUs (AFAIK) using this technology. You expect AMD to go all out on something new and complex. Seriously, you are like a dog with a bone. If you want to die on this hill - that's your choice; but I think you are 100% off base.

AMD already has a high end CPU for MT in 5950X. Gamers are not super interested in this one.

Lots of high-end gamers, also buy 5950Xs.

 

[CHADBOGA]

They ARE adding V-Cache for gamers, but it's a cutting edge technology. These will be their first CPUs (AFAIK) using this technology. You expect AMD to go all out on something new and complex. Seriously, you are like a dog with a bone. If you want to die on this hill - that's your choice; but I think you are 100% off base.

At least he isn't saying that AMD should use SMT4

 

[Thibsie]

At least he isn't saying that AMD should use SMT4

Oh please, no !

 

[Joe NYC]

Rather than aim for multi-layer V-Cache in the mainstream, which may be difficult to do due to cost and sparse capacity, perhaps we'll see the gaming crown move to HEDT. I guess AMD would love to say that their upcoming Threadrippers make no compromises — with lots of "Zen 3" cores, high clock speed, huge memory bandwidth, and copious amounts of cache.

I think Threadripper as a gaming platform is not a good idea. The main theme behind Threadripper is "Thread Ripper", meaning MT performance, which is the opposite end of the spectrum of gaming CPU. And cost of the platform makes it a non-starter.

It seems that every CPU AMD is offering right now has an element that keeps it from being a fully optimized for gaming:

5800x:
+ closest to ideal, acceptable price
- not using the best binning dies
- IOD-CCD connection not ideal for gaming, limits overclocking, limits maxing out the memory

5950:
+ highest binning dies
- not fully maxed out because of power limit on 16 cores
- high cost
- wasted 2nd CCD
- extra memory coherency between CCDs
- IOD-CCD link see above

Cesanne:
+ good price
+ no IOD-CCD
+ good for overclocking and maxing out memory
- 65W limit
- 16 MB L3

Threadripper:
- everything

It would be interesting if AMD could add V-Cache to Cezanne, tune it it for high clock speed and 105W.

2nd choice would be to max out 5800x with highest bin dies and max V-Cache.