Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Markfw]

Question. If the Raptor Lake 13900k has 16 big cores and 8 weak little cores. If the numbers (big performance in Cinebench and some other benchmarks) are true. We don't know the Zen 4 performance of the 7950x. The performance leaks are at 240w for the 13900k but they also have better specs in complete unlimited power guzzling 450-500w. I know Zen 4 is increasing the TDP of Zen 4 processors but I do not think Zen 4 will get anywhere near Raptor Lake power usage.

Is it possible we could see a 24core or 32core Zen 4 CPU? I have been told no. But 5nm gives more real estate on the die vs. 7nm on Zen 3. Why are we not seeing potentially higher core counts for Zen 4? It makes no sense to me. 5nm vs. 10nm for Intel.
Dr. Su said that AMD would add more cores for a core war with Intel in the past.

Lastly is AMD happy with the scaling of 5nm vs. 7nm? I think they were hoping for more performance boost with the node shrink. Then we have 3nm for Zen 5 if TSMC can pull it off. Then Intel has 7nm on whatever they release after Raptor Lake. Unlike AMD and their well defined road map. Intel scraps plans and makes new cores and designs on the fly.

If Zen 4 were released near the beginning of 2022 it would be a big win for AMD. Instead AMD is allowing Intel to catch up. I know many of you think AMD is ahead of Intel. Since Alder Lake they are behind Intel except for power efficiency. Obviously on the server side Zen 4 will totally smoke Raptor Lake.

Raptor lake has 8 BIG and 16 little cores. And Alder Lake is only ahead of Zen 3 in some areas, like single core or low core count tasks. Anything that uses 8 cores or less, they are better than Zen 3. In full multicore (as in long running 16 or more threads) Zen 3 shines.

 

[gdansk]

Question. If the Raptor Lake 13900k has 16 big cores and 8 weak little cores.

You have that backward.

Is it possible we could see a 24core or 32core Zen 4 CPU? I have been told no. But 5nm gives more real estate on the die vs. 7nm on Zen 3. Why are we not seeing potentially higher core counts for Zen 4? It makes no sense to me. 5nm vs. 10nm for Intel.

Zen 4 CCD only ended up slightly smaller (maybe 10mm² less). They decided to go with absurd power limits like Intel. It costs them nothing where as adding a 3rd CCD would increase the BOM.

And I'd debate Alder Lake is really ahead except because of AMD limiting itself. A 5950X3D would be comparable in games and better than ADL in MT. Yet they didn't make it. This time it seems likely AMD will have a 7950X3D available soon.

 

[Joe NYC]

Question. If the Raptor Lake 13900k has 16 big cores and 8 weak little cores. If the numbers (big performance in Cinebench and some other benchmarks) are true. We don't know the Zen 4 performance of the 7950x. The performance leaks are at 240w for the 13900k but they also have better specs in complete unlimited power guzzling 450-500w. I know Zen 4 is increasing the TDP of Zen 4 processors but I do not think Zen 4 will get anywhere near Raptor Lake power usage.

Is it possible we could see a 24core or 32core Zen 4 CPU? I have been told no. But 5nm gives more real estate on the die vs. 7nm on Zen 3. Why are we not seeing potentially higher core counts for Zen 4? It makes no sense to me. 5nm vs. 10nm for Intel.
Dr. Su said that AMD would add more cores for a core war with Intel in the past.

Lastly is AMD happy with the scaling of 5nm vs. 7nm? I think they were hoping for more performance boost with the node shrink. Then we have 3nm for Zen 5 if TSMC can pull it off. Then Intel has 7nm on whatever they release after Raptor Lake. Unlike AMD and their well defined road map. Intel scraps plans and makes new cores and designs on the fly.

If Zen 4 were released near the beginning of 2022 it would be a big win for AMD. Instead AMD is allowing Intel to catch up. I know many of you think AMD is ahead of Intel. Since Alder Lake they are behind Intel except for power efficiency. Obviously on the server side Zen 4 will totally smoke Raptor Lake.

AMD sees distribution of sales of desktop processors by core count (6, 8, 12, 16). If the sales of the 16 core not low single digits, but, say 35%, AMD would surely consider higher core counts.

But if it is low single digits, there is not much justification to go beyond 16 cores for desktop at this time.

 

[Hans Gruber]

Raptor lake has 8 BIG and 16 little cores. And Alder Lake is only ahead of Zen 3 in some areas, like single core or low core count tasks. Anything that uses 8 cores or less, they are better than Zen 3. In full multicore (as in long running 16 or more threads) Zen 3 shines.

I personally think Zen 3 is a huge upgrade over Zen 2. I get 500-600mhz on Zen 3. It runs games much better than Zen 2. They fixed the memory latency issue that plagued Zen 2 performance.

I think the stacked 3D cache will be much better on Zen 4. There will not be a max clock issue like with Zen 3 for 3d stacked chips.

 

[coercitiv]

Zen 4 CCD only ended up slightly smaller (maybe 10mm² less).

On top of that AMD made design decisions that severely limit room for additional chiplets on AM5, in order to ensure backwards mechanical compatibility with AM4 socket (area, retention mechanism geometry). The strange IHS shape is the result of this compromise.

Later edit: here's a simulation using overlapped images from AMD, this way we can see the room available under the IHS.

And I'd debate Alder Lake is really ahead except because of AMD limiting itself.

They could have gone further indeed, but at the same time they did enough to keep the wind in their favor:



Intel was unable to take full advantage of their Alder Lake launch, and AMD was able to reverse the market trend by combining a successful 5800X3D launch with relaxed pricing in the rest of their consumer lineup. The mind share they were able to gain in the last few years paid dividends in full, even with Intel offering an arguably faster core & competitive pricing.

 

[ondma]

On top of that AMD made design decisions that severely limit room for additional chiplets on AM5, in order to ensure backwards mechanical compatibility with AM4 socket (area, retention mechanism geometry). The strange IHS shape is the result of this compromise.


They could have gone further indeed, but at the same time they did enough to keep the wind in their favor:

View attachment 65699

Intel was unable to take full advantage of their Alder Lake launch, and AMD was able to reverse the market trend by combining a successful 5800X3D launch with relaxed pricing in the rest of their consumer lineup. The mind share they were able to gain in the last few years paid dividends in full, even with Intel offering an arguably faster core & competitive pricing.

Do they still include console in the x86? That could skew the numbers somewhat. The cost advantage still probably goes to AMD though, considering Zen 3 is a drop in to older motherboards and uses DDR4 while Alder Lake requires DDR5 for optimal performance, as well as a new motherboard.

 

[coercitiv]

Do they still include console in the x86?

I was primarily focused on Desktop data in the context of the Alder Lake launch.

However, regarding the x86 datam Tom's Hardware mentions it does indeed include consoles:

Whereas other segments exclude IoT and semi-custom (like AMD's game console business), this accounting of the overall x86 market also includes those products and is focused primarily on the broader AMD vs Intel competition.

 

[maddie]

Question. If the Raptor Lake 13900k has 16 big cores and 8 weak little cores. If the numbers (big performance in Cinebench and some other benchmarks) are true. We don't know the Zen 4 performance of the 7950x. The performance leaks are at 240w for the 13900k but they also have better specs in complete unlimited power guzzling 450-500w. I know Zen 4 is increasing the TDP of Zen 4 processors but I do not think Zen 4 will get anywhere near Raptor Lake power usage.

Is it possible we could see a 24core or 32core Zen 4 CPU? I have been told no. But 5nm gives more real estate on the die vs. 7nm on Zen 3. Why are we not seeing potentially higher core counts for Zen 4? It makes no sense to me. 5nm vs. 10nm for Intel.
Dr. Su said that AMD would add more cores for a core war with Intel in the past.

Lastly is AMD happy with the scaling of 5nm vs. 7nm? I think they were hoping for more performance boost with the node shrink. Then we have 3nm for Zen 5 if TSMC can pull it off. Then Intel has 7nm on whatever they release after Raptor Lake. Unlike AMD and their well defined road map. Intel scraps plans and makes new cores and designs on the fly.

If Zen 4 were released near the beginning of 2022 it would be a big win for AMD. Instead AMD is allowing Intel to catch up. I know many of you think AMD is ahead of Intel. Since Alder Lake they are behind Intel except for power efficiency. Obviously on the server side Zen 4 will totally smoke Raptor Lake.

Unlike AMD and their well defined road map. Intel scraps plans and makes new cores and designs on the fly.

This is priceless. After watching the Intel Titanic trying & failing to change course for years, I read this.

Picture the Intel elephant dancing around AMD.

 

[Hans de Vries]

On top of that AMD made design decisions that severely limit room for additional chiplets on AM5, in order to ensure backwards mechanical compatibility with AM4 socket (area, retention mechanism geometry). The strange IHS shape is the result of this compromise.

Later edit: here's a simulation using overlapped images from AMD, this way we can see the room available under the IHS.
View attachment 65700

I would argue that there is enough room for extra dies and the capacitors. This is a mock-up from 9 months ago on this thread.

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[maddie]

I would argue that there is enough room for extra dies and the capacitors. This is a mock-up from 9 months ago on this thread.

View attachment 65701

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Is space for die placement the space that is limited or space for signal traces?

I remember AMD, in an interview, outright saying that routing the various signals between the chiplets and the IOD was a difficult engineering problem given the small space and sounding proud in having solved it well. That was for 2 chiplets.

 

[biostud]

I don't think we'll see more than two chiplets, mainly because the market for a desktop with 24 or 32 cores is incredible small.

Zen5 could bring more cores, but with rumors of Zen4 cores on the IOD, Zen4c mixed with zen5, all bets are off.

 

[Joe NYC]

Is space for die placement the space that is limited or space for signal traces?

I remember AMD, in an interview, outright saying that routing the various signals between the chiplets and the IOD was a difficult engineering problem given the small space and sounding proud in having solved it well. That was for 2 chiplets.

I think that was in reference to 2 chiplets, one behind the other, as in group of 2, 4 groups for total of 8 chiplets, in Epyc.

This would be similar to group of 2, one behind the other in Hans's diagram, although the 2 groups are much more tightly packed.

 

[Mopetar]

I think they should drop the Ry part and just call it Zen 4.

They can't trademark Zen so there's nothing they could do about stopping any shady outfits from marketing their products that way. Ryzen is their trademark, so that's why they just let Zen be the code name.

It's the same reason that Intel started using the Pentium branding. They found out that they couldn't actually trademark their CPUs if they were just a number (e.g. 8008, 486, etc.) so they started using Pentium since it was the 586 they adopted the branding for.

 

[Mopetar]

I would argue that there is enough room for extra dies and the capacitors. This is a mock-up from 9 months ago on this thread.

View attachment 65701

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You'd need a whole new IO die (that would also be larger) to be able to connect to the additional chiplets. The added costs for the design and masks means they'd either need to sell a lot of these parts or would have to charge a premium for them.

If they do offer more than 16C/32T this generation it will be through hooking up Zen 4c chiplets which have additional cores. They might go down that route if there's a competitive need and they don't want to or aren't able to address that part of the market with Threadripper.

 

[burninatortech4]

I don't think we'll see more than two chiplets, mainly because the market for a desktop with 24 or 32 cores is incredible small.

Zen5 could bring more cores, but with rumors of Zen4 cores on the IOD, Zen4c mixed with zen5, all bets are off.

Why would there be Zen4 cores on the IOD?

 

[biostud]

Why would there be Zen4 cores on the IOD?

I can’t find where I saw the rumor/speculation (or maybe I just remember something wrong, which is likely)

 

[NostaSeronx]

I can’t find where I saw the rumor/speculation (or maybe I just remember something wrong, which is likely)

I posted that. So far no one else found the origin for it yet: https://forums.anandtech.com/thread...ryzen-7000-etc.2571425/page-278#post-40814470

Why would there be Zen4 cores on the IOD?

Zen5's IOD was going to share the same die with Zen4's cIOD. Howver, it appears to have been swapped out for N4 w/ Zen4.

1x CCX of Zen4 (AVX512)+ Up to 2x CCX of Zen5 (AMX)

There is suppose to be more Z-states and hardware state control, etc.

Zen4 cores handle background/system at low-latency/low-power: immediate access to DRAM and NVMe.
Zen5 cores handle foreground at high-performance/high-throughput: slower GMI/IFOP but much larger L3 cache.

In this case, idle workloads don't wake up Zen5 cores. Only used in active workloads in foreground, etc.

If discrete GPU in on, then Zen5 is preferred. So far all I can find is it is basically SmartShift for desktop/chiplet design.

Zmin through Zlowpeak: whatever the Zen4+RDNA TDP is in the N4 SOC.
Zavg through Zpeak: standard TDP of CCDs+SoC.

 

[AAbattery]

I can’t find where I saw the rumor/speculation (or maybe I just remember something wrong, which is likely)

A possible reason is that it would save designing another chip if they could reuse it as a low-power APU design, if they found a way to use the Zen 4 cores without scheduling issues when used as an IO die, paired with a Zen 5 CCD.

 

[igor_kavinski]

Intel is so screwed if AMD's E-core is gonna be a Zen 4 core. Intel would need at least an Ice Lake powered E-core to compete.

 

[Saylick]

A possible reason is that it would save designing another chip if they could reuse it as a low-power APU design, if they found a way to use the Zen 4 cores without scheduling issues when used as an IO die, paired with a Zen 5 CCD.

So it would be like present day AMD APUs except that they include a pair of IFOP PHYs for the two Zen 5 CCDs? I'm guessing it would be an APU variant that is designed for the lower end (read: 8 cores max, smaller iGPU) since if they literally take their high-end mobile SOC and use that as an IOD, the desktop package probably gets expensive since you'd essentially be paying for a mobile processor with every desktop CPU purchase.

 

[.vodka]

Is space for die placement the space that is limited or space for signal traces?

I remember AMD, in an interview, outright saying that routing the various signals between the chiplets and the IOD was a difficult engineering problem given the small space and sounding proud in having solved it well. That was for 2 chiplets.

That statement was made in context of having to deal with AM4's original restrictions. It started out with single chips (Bristol Ridge, Summit Ridge, Pinnacle Ridge) then transitioned to chiplets.

AM5 has been designed from the ground up with chiplets in mind. We've already seen Genoa delidded with its 12 CCDs, this time the chiplets are literally side by side. Zen2/Zen3 CCDs in previous generations had never been packed so tightly neither in AM4 nor SP3. Of course, 8 vs 12 CCDs, but still, the package can handle such tight placement if needed.

Considering the more advanced packaging possible this generation, Hans' mockup could very well be possible on AM5 if the I/O die has more than 2 links for CCDs.

 

[nicalandia]

Looking at the AES scores, it is clear that AVX-512 is playing a part in the ES

Yes, it sound about right..

The AES-XTS workload in Geekbench 5 encrypts a 128MB buffer using AES running in
XTS mode with a 256-bit key. The buffer is divided into 4K blocks.

It is becoming clear that AMD Overall design choices and Intel bad implementation of their Golden Cover uArch on Xeons will pay dividend for AMD AVX-512 Performance at the High End HPC/AI segment.

QS/Release sample of a 56C/112T Sapphire Rapids getting mauled at AVX-512 by a 32C/64T Genoa

 

[Joe NYC]

I posted that. So far no one else found the origin for it yet: https://forums.anandtech.com/thread...ryzen-7000-etc.2571425/page-278#post-40814470Zen5's IOD was going to share the same die with Zen4's cIOD. Howver, it appears to have been swapped out for N4 w/ Zen4.

1x CCX of Zen4 (AVX512)+ Up to 2x CCX of Zen5 (AMX)

There is suppose to be more Z-states and hardware state control, etc.

Zen4 cores handle background/system at low-latency/low-power: immediate access to DRAM and NVMe.
Zen5 cores handle foreground at high-performance/high-throughput: slower GMI/IFOP but much larger L3 cache.

In this case, idle workloads don't wake up Zen5 cores. Only used in active workloads in foreground, etc.

If discrete GPU in on, then Zen5 is preferred. So far all I can find is it is basically SmartShift for desktop/chiplet design.

Zmin through Zlowpeak: whatever the Zen4+RDNA TDP is in the N4 SOC.
Zavg through Zpeak: standard TDP of CCDs+SoC.

I could buy this as a concept, but I don't believe that the die with I/O (and the Zen4 core) would be on N4 rather than N6.

 

[Thibsie]

They can't trademark Zen so there's nothing they could do about stopping any shady outfits from marketing their products that way. Ryzen is their trademark, so that's why they just let Zen be the code name.

It's the same reason that Intel started using the Pentium branding. They found out that they couldn't actually trademark their CPUs if they were just a number (e.g. 8008, 486, etc.) so they started using Pentium since it was the 586 they adopted the branding for.

Well, an obscure unknown company managed to protect the Windows name so who knows...

 

[Thibsie]

You'd need a whole new IO die (that would also be larger) to be able to connect to the additional chiplets. The added costs for the design and masks means they'd either need to sell a lot of these parts or would have to charge a premium for them.

If they do offer more than 16C/32T this generation it will be through hooking up Zen 4c chiplets which have additional cores. They might go down that route if there's a competitive need and they don't want to or aren't able to address that part of the market with Threadripper.

Who said the current IOD was unable to work with more than two chiplets ?
If AMD planned for more than two chiplets, they probably built it already.

If they didn't, it for good reasons, meaning they either don't need more than two chiplets or the chiplet will change anyway with zen5 or something along those lines...