Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

Vattila

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Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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soresu

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Dec 19, 2014
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igor_kavinski said:
Remember, AMD themselves did not discount the possibility of future CPUs on AM4. They said that it will co-exist with AM5 for a while.
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To quote a famous vengeful Spaniard I do not think that means what you think it means.... 😄

All it means for sure is that they will continue to manufacture previously announced chipsets and CPUs/APUs for the AM4 platform for an undisclosed amount of time after AM5 products become available.

Nothing about that information implies that there will be new products on AM4.
 
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LightningZ71

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The WSA still exists. They still have to run the wafers. I don't see declining Milan volumes, declining zen3 volumes and Chromebook chips keeping it busy. The recently introduced embedded refresh of Picasso isn't likely to demand a lot of revenue either.

I don't think that ZEN4 on AM4 is realistic though. I find an N6 respin of Zen3 to be more applicable, but also unlikely.
 
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Thunder 57

Thunder 57

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soresu said:
To quote a famous vengeful Spaniard I do not think that means what you think it means.... 😄

All it means for sure is that they will continue to manufacture previously announced chipsets and CPUs/APUs for the AM4 platform for an undisclosed amount of time after AM5 products become available.

Nothing about that information implies that there will be new products on AM4.
Click to expand...

I totally forgot about that guy. What was his name?
 
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eek2121

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LightningZ71 said:
The WSA still exists. They still have to run the wafers. I don't see declining Milan volumes, declining zen3 volumes and Chromebook chips keeping it busy. The recently introduced embedded refresh of Picasso isn't likely to demand a lot of revenue either.

I don't think that ZEN4 on AM4 is realistic though. I find an N6 respin of Zen3 to be more applicable, but also unlikely.
Click to expand...

This might surprise you, but AMD still has plenty of business with GloFo. Lots of low end parts are either on 14nm/12nm, or use it in some way. Not to mention that they still sell boatloads of Rome and Milan chips (edit: as well as Threadripper), and will for the foreseeable future.

The enthusiast/high end market is one small piece of a much larger pie.
 
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igor_kavinski

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Timorous said:
Zen4 on AM4 would make Genoa possible on the current server platform using the server IO die.
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AMD can make a lot of enterprise customers happy that way. Think of how bad that would make Intel look who normally expect customers to throw out their old servers and buy new ones for a CPU generational upgrade.
 
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Mopetar

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Abwx said:
Or to fullfill the WSA with GF since there s nothing left from this foundry in the next gen DT CPUs.
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They're probably still doing the IO dies for the server chips. With AMD adding a minimalist GPU to Zen 4 desktop, using TSMC makes more sense, especially considering that they would have already done the design work for their APUs and could reuse that.

There was also some speculation that GF would be used to make HBM for AMD. The kind of purchases that AMD made aren't nearly enough to just cover IO dies for Milan. Future products would need to use GF as well for the numbers to make any kind of sense.
 
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Abwx

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Mopetar said:
They're probably still doing the IO dies for the server chips. With AMD adding a minimalist GPU to Zen 4 desktop, using TSMC makes more sense, especially considering that they would have already done the design work for their APUs and could reuse that.

There was also some speculation that GF would be used to make HBM for AMD. The kind of purchases that AMD made aren't nearly enough to just cover IO dies for Milan. Future products would need to use GF as well for the numbers to make any kind of sense.
Click to expand...

On second thoughts the automotive market is low margin and doesnt require the latest process, Tesla is using Zen+ in their cars, and AMD has other customers willing to buy whatever is at disposal given that shortages in this industry are still going on.
 
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NostaSeronx

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Sep 18, 2011
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AMD's Wafer Supply Agreement with GlobalFoundries for older products is to secure supply.

Naples = Low Volume
Rome = Low Volume
Milan/Milan-X = Low Volume when Genoa/Genoa-X/Bergamo/Siena comes out.
R2000 = Low Volume
R1000 = Low Volume
V1000 = Low volume especially with V2000/V3000 series.
EPYC Embedded = 2023 (first flush of EOL), 2024 (second flush of EOL)
1000s = 2-year full+1-year half support (2017+3 = EOL)
2000s = (2018+3 = EOL)
3000s = (2019+3 = EOL)
etc./etc.

Newer products always reduce the volume of the prior products. Wafer supply agreement prefers investments into newer products not older released products.

2021 WSA:
- Supply Assurance of the above products (Pre-ordered)
- Increased partnership of not the above products (Pre-ordered)

Phase 1/2 of 2023 = Supply Assurance (P1=first half, P2=second half)
Phase 3 of 2023 = Partnership (P3=second half)

Phase 3 = New products on tailored nodes (Ex of prior tailored nodes: AMD's 28nm GF28A + AMD's 20nm GF20AN)
Malta products => https://ieeexplore.ieee.org/document/9771014 (18-21 April 2022) with it tailored to AMD product.
 
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jamescox

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Mopetar said:
They're probably still doing the IO dies for the server chips. With AMD adding a minimalist GPU to Zen 4 desktop, using TSMC makes more sense, especially considering that they would have already done the design work for their APUs and could reuse that.

There was also some speculation that GF would be used to make HBM for AMD. The kind of purchases that AMD made aren't nearly enough to just cover IO dies for Milan. Future products would need to use GF as well for the numbers to make any kind of sense.
Click to expand...
A google search for Global Foundries and HBM does turn up some articles about them making HBM2e, like this one:

www.anandtech.com

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

www.anandtech.com www.anandtech.com

This is from 2019 saying that it will be ready by 2020. Perhaps there was some Covid 19 delays though. It seems plausible that GF my be used as a source for HBM. If you look at AMD’s upcoming products, they will need a massive increase in HBM supply. I am wondering if GF has a process capable of making SRAM cache chips also. The 3D stacked things AMD has shown seem more likely to be using EFB-style connections for cache chips under the compute die rather than SoIC. The SoIC stuff needs to be made at TSMC, but things connected by EFB-style connections are micro-solder ball base and can be made at other fabs.
 
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MadRat

MadRat

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If they are running stacked chips it would make perfect sense to use the chiplets with the lowest thermal generation. Using older processes for the cache simply compounds thermal issues and requires locating the cache further from the core. You want the shortest possible trace paths.
 
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jamescox

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MadRat said:
If they are running stacked chips it would make perfect sense to use the chiplets with the lowest thermal generation. Using older processes for the cache simply compounds thermal issues and requires locating the cache further from the core. You want the shortest possible trace paths.
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I don’t know if GF processes are sufficient for cache chips. AMD will need some other chips though. I was looking at the Trento diagrams which seem to have 2 gpu chips and 8 HBM per package. I have seen some diagrams that seem to indicate that it has essentially 4 IFOP style connections between GPUs and it also has doubled up x16 links between all 4 GPUs and each gpu to the cpu. This seems to require something like 4 IFOP style links and 4 IFIS style links per GPU (2 per package), which is kind of half of what a Rome / Milan IO die requires.

I am wondering if there will be a modular IO die with something like 4 IFOP and 4 IFIS. The next gen devices seem to go with smaller gpu chip with a single stack of HBM each, perhaps utilizing HBM 3. The diagrams I have seen seem to show two combined gpu chiplets (maybe one cpu one gpu in some products) likely combined with silicon bridges. Likely also silicon bridges to HBM, but they appear to far apart for silicon bridges between the modules, so perhaps that is many IFOP style connections. If they do have such a modular IO die, then Bergamo may use 2 of them, hence the 8 cpu chiplet limit. I don’t know if they would put DDR5 controllers on the same die or split that off into a separate chip also.
 
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CakeMonster

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Rumors have been ridiculous the last couple of days. I would not get my hopes up for the most outlandish stuff.

V-Cache releases could come earlier, but unless AMD confirms it I would not count on waiting for something that may never arrive (like the non-8c models).
 
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Mopetar

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Is the 100MB just rounding up the 96 MB (32 + 64) that it's expected to have or is there some other reason for that number?

I'm not even sure this qualifies as a rumor given AMD has told us to expect Zen 4D this year. Since they need Zen 4 chiplets to stack v-cache on and Zen 4 is expected to launch in/around September, it seems obvious that the chiplets would need to be in the production stage.
 
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Timmah!

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If they now say the 3D versions will come before the end of the year, is it not possible they may actually launch alongside the non v-cache versions? Or at very least be announced/revealed at the same time, with availability say month or 2 later than the vanilla versions?
 
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