Speculation: Ryzen 4000 series/Zen 3

[DrMrLordX]

How quickly is Intel iterating on their architectures, how about ARM Neoverse?

Very slowly. That's the exact opposite of what AMD needs to do, and it offers them an amazing opportunity. Milan/Vermeer will be a major step up for AMD while Intel has nothing outside of 4c mobile chips. IceLake-SP still isn't here. After massive delays. Why isn't anyone gunning for Bob Swan's head at this point?

Rushing with releases is a huge risk that they shouldn’t take.

I'm not suggesting "rushing". AMD did quite well for itself between 2017-2018 on a 13-14 month release cycle; granted, Pinnacle Ridge was a relatively minor release, but they did manage to execute very well with it, on a relatively short timeline. To whit, they managed to release Pinnacle Ridge 13 months after Summit Ridge while they managed to release Picasso maybe 11 months after Raven Ridge? I forget when Raven came out exactly, but Picasso was January 2019.

Imagine this timeline:

I can stop you right there and remind you that the semicon industry moves much faster than anything else. What seems unachievable elsewhere is achievable in semicon. So moving from Zen1 to Zen4 can't be thought of as moving from an R7 rocket to a space elevator. Completely different scales of phenomena.

It's well within AMD's capabilities to have Zen4 ready in 2021. Due to the way market windows work (that is to say, they want to give Zen3 products enough time to sell through to recoup development and show a profit), there's no way AMD can feasibly move to Zen4 that quickly now. They would essentially be oprhaning their own product. Moving beyond Zen4 . . . we don't know. That hasn't shown up on any roadmaps yet (that I've seen) and there may be very good reasons for that. I don't even know if the working group for Zen5 is yet convened. The working group for Zen4 has been operating for some time now, and it's reasonable to expect that they'll show results soon. They may even be ready to start sampling chips by the end of this year, or whenever they can get some 5nm test wafers from TSMC.

Not really. K8 Opteron was an absolutely massive success from AMD and basically pushed them from 0% to 25% of server and datacenter market share in a little over 2 years. The problem was they had no real follow up to K8 after 3 years.

That's exactly what I'm saying. Despite the massive success, AMD still wound up on the rocks. They had no follow-up. They kept milking the same underlying uarch for far too long, thanks in no small part to Hector Ruiz (also, anyone remember the old K9 and K10 project(s) that never saw the light of day?).

The good thing is for AMD now is that Zen3 is here and Zen4 is on the (admittedly distant) horizon. The underlying designs are there or will be there. The process tech is already in place; TSMC is in full production on 5nm as we speak. The only thing that has to happen is for AMD to get stuck on one particular uarch again for too long. Then bad things may happen. Or if they don't, AMD gets to rehash endlessly at our expense. They get to become the monster we always hoped they'd slay.

Zen on the other hand is already on its 3rd major revision/overhaul in just over 3 years. AMD is iterating fast, and is not sitting on their laurels.

The XT launch = resting on their laurels. If Warhol is real, then in a way that also amounts to resting on their laurels.

The only way AMD is "becoming like Intel" right now, that they're working on delivering more polished platforms and processors.

They're also driving up prices. Don't pretend that they aren't.

You see and hear about ARM startups like Nuvia and others who are apparently developing their chips at a fever pace.

Honestly I don't know whether I believe any of that hype. Lots of talk, but not a lot of action.

I wasn't referring to you. I was referring to Sir Richard of the Four Realms.

Ah yes, him . . .

What? You were suggesting AMD release a processor every 12 months and not way upwards of 18 months.

If it's a substantial launch, then yes. And they certainly seem capable of doing so. The fab tech is there, the working groups are hitting their milestones. Only thing that seems lacking is firmware support.

And that they should include refreshes. All for the same ASP. How is that not like Intel?

You've got me all wrong. I don't like the product refreshes, not one bit. Not XT, not hypothetical Warhol. I 'd rather they didn't exist.

Intel may not be running on all cylinders compared to a decade ago but they certainly are not standing completely still, and AMD still need to fight to get market share in areas currently dominated by them - Renoir is just the first real opening salvo towards biting into NUC and assorted laptop segments, they are not even close to a significant piece of the pie there as yet.

Preaching to the choir. Sadly, I do not think AMD will get that market share by slowing down to an 18 month cadence from 15-month or 13-month. I don't see that the industry saying, "you need more spit-polish on your enterprise designs and platforms", I see them saying, "your Rome product is compelling, but due to problems with our hypervisor software and/or Intel bribing us through trusted vendors that our COO insists on working with, we won't buy your hardware anyway. We'll look at you again when the TCO gap is so enormous that we can't justify using Intel hardware even if they give it to us for free".

Until AMD have a dramatic cut of market share in all segments they compete with Intel for I don't expect to see them purposefully holding back on new products for any reason other than maximizing ROI from their current product R&D, which is extremely important for a company like AMD that doesn't have a humongous war chest to fall back on.

There are limits to how long any one design should be left on the market in semicon. The constant drive forward to new designs and new levels of performance is why we're all here. Matisse has been on shelves for 16 months now, and Vermeer may go beyond 18 months if it gets rehashed as Warhol (gag). Even if you would think that AMD wouldn't purposefully hold back on products, there's the possibility that they're doing it already. Those shareholders will want to see revenue. Especially the ones who bought near the top.

 

[HurleyBird]

Why isn't anyone gunning for Bob Swan's head at this point?

Most likely it's because no one wants to take his place. Or to be more exact, no one wants to take his place yet. Given the option, you don't replace the lame duck CEO while the ship is still sinking. You replace the lame duck CEO just before the ship is about to right itself, after which the new CEO takes the credit even if he had nothing to do with it.

 

[Thunder 57]

I can stop you right there and remind you that the semicon industry moves much faster than anything else. What seems unachievable elsewhere is achievable in semicon. So moving from Zen1 to Zen4 can't be thought of as moving from an R7 rocket to a space elevator. Completely different scales of phenomena.

It's well within AMD's capabilities to have Zen4 ready in 2021. Due to the way market windows work (that is to say, they want to give Zen3 products enough time to sell through to recoup development and show a profit), there's no way AMD can feasibly move to Zen4 that quickly now. They would essentially be oprhaning their own product. Moving beyond Zen4 . . . we don't know. That hasn't shown up on any roadmaps yet (that I've seen) and there may be very good reasons for that. I don't even know if the working group for Zen5 is yet convened. The working group for Zen4 has been operating for some time now, and it's reasonable to expect that they'll show results soon. They may even be ready to start sampling chips by the end of this year, or whenever they can get some 5nm test wafers from TSMC.

The space elevator was more of a joke compared to the rest but do remember that it was a "Space Race". Things were happening very rapidly back then. But things still take time.

I think a better argument to make is why did Zen+ have to exist? Because then we'd be on Zen 3 today with Zen 4 coming shortly. That seems to fit your cadence better. My guess is that AMD was so resource strapped that it couldn't follow up like it can now. They were also still working out the oddities of the new platform. Zen+ is what Zen should have been. Not to say Summit Ridge was bad though.

Now AMD has the luxury of deciding when to ship Zen 4 to an extent, as you said. I just hope that AMD remembers what happened last time they were on top. I think AMD's future is still bright with Lisa Su in charge.

 

[DrMrLordX]

Most likely it's because no one wants to take his place. Or to be more exact, no one wants to take his place yet. Given the option, you don't replace the lame duck CEO while the ship is still sinking. You replace the lame duck CEO just before the ship is about to right itself, after which the new CEO takes the credit even if he had nothing to do with it.

A bit off topic, but it would be fun to speculate as to how Koduri could parlay this situation into becoming Intel's next CEO. Maybe in some other thread.

I think a better argument to make is why did Zen+ have to exist?

I've kind of wondered about that one myself.

The initial Zen team went as far back as 2012 when they hired Keller to build a team for a next-gen product. It took them five years to get ideas into working, commercially-available silicon. Five years. That's a long time, and it ought to tell you something about the state of AMD's CPU development team(s) in 2010-2012; that is, to say, they weren't doing very well at all.

Compare that to late 2018 when Rome was sampling and late 2019 when Milan was sampling, and you have a situation where AMD was able to move from Rome QS -> Milan QS in ~12 months. A massive improvement. Granted, Rome and Milan aren't so distant from one another in underlying design compared to Piledriver and Naples. Most of the groundwork for Milan has been laid out in the previous two generations of Zen. The question is, why the 2+ year delay between Naples and Rome?

I think it has more to do with when teams were put together and under what circumstances. AMD had major debt and not very much revenue in 2012, so Zen had to be developed on a comparatively shoestring budget. Eventually AMD convened teams for update products, and if I recall correctly, the teams were put together at about the same time. The teams were assigned to Zen2, Zen3, and Zen4, to keep the updates coming and keep AMD relevant at least as far out as 2021. Those dates have slipped a little into 2022.

In any case, with Zen, there was no guarantee of success or a future. There were also revenue problems until Ryzen and Naples CPUs could start selling. The Zen2 team may have taken as long as they did to produce working silicon due merely to resource starvation. It probably took over half a year or more of selling Zen to start seeing an appreciable uptick in usable cash-on-hand. AMD knew they couldn't ride Summit Ridge forever, so Zen+/Pinnacle Ridge was a cheap replacement for a product update. Cash flow may well have negatively affected all three of the Zen update teams. Also remember that AMD was stalled out by Globalfoundries and their failure to make 7nm work. AMD had (allegedly) already planned to move Rome to TSMC N7 (along with Vega20) well before GF threw in the towel, but that doesn't tell the entire story. In theory, had GF gotten their 7nm ducks in a row, we could have seen Matisse on GF 7nm much earlier than we saw Matisse on TSMC 7nm. In fact, at the time, that was one of my main assumptions as to why Matisse had taken so long and why we ever saw Pinnacle Ridge in the first place: in 2018, GF couldn't guarantee 7nm to AMD at any future point, so it was easier to sell a Pinnacle Ridge product on an improved GF 12nm process than it was to try and get Matisse to market ASAP. AMD also had a WSA to fulfill. That wasn't re-negotiated until GF proved they couldn't hold up their end of the bargain.

Kinda makes you wonder what process targets the Zen3 and 4 teams had before AMD knew that GF would go bust.

So, to summarize, I think Pinnacle Ridge happened because:

Cash flow made it difficult for the Zen2/3/4 teams to work at full pace until sales of Zen stabilized revenue
Zen2 was never going to be ready before Q4 2018 in any form (QS or otherwise) as result
GF couldn't guarantee a process for Zen2, but they could tweak 14nm into 12nm for an "easy" filler product

The confluence of factors made it inevitable that AMD would need Pinnacle Ridge. Note that Pinnacle Ridge was never used for EPYC. Now that AMD has a stable fab and has had decent-to-good cash flow for 2+ years now, there should be no further need for Pinnacle Ridge-like products.

 

[jamescox]

A bit off topic, but it would be fun to speculate as to how Koduri could parlay this situation into becoming Intel's next CEO. Maybe in some other thread.



I've kind of wondered about that one myself.

The initial Zen team went as far back as 2012 when they hired Keller to build a team for a next-gen product. It took them five years to get ideas into working, commercially-available silicon. Five years. That's a long time, and it ought to tell you something about the state of AMD's CPU development team(s) in 2010-2012; that is, to say, they weren't doing very well at all.

Compare that to late 2018 when Rome was sampling and late 2019 when Milan was sampling, and you have a situation where AMD was able to move from Rome QS -> Milan QS in ~12 months. A massive improvement. Granted, Rome and Milan aren't so distant from one another in underlying design compared to Piledriver and Naples. Most of the groundwork for Milan has been laid out in the previous two generations of Zen. The question is, why the 2+ year delay between Naples and Rome?

I think it has more to do with when teams were put together and under what circumstances. AMD had major debt and not very much revenue in 2012, so Zen had to be developed on a comparatively shoestring budget. Eventually AMD convened teams for update products, and if I recall correctly, the teams were put together at about the same time. The teams were assigned to Zen2, Zen3, and Zen4, to keep the updates coming and keep AMD relevant at least as far out as 2021. Those dates have slipped a little into 2022.

In any case, with Zen, there was no guarantee of success or a future. There were also revenue problems until Ryzen and Naples CPUs could start selling. The Zen2 team may have taken as long as they did to produce working silicon due merely to resource starvation. It probably took over half a year or more of selling Zen to start seeing an appreciable uptick in usable cash-on-hand. AMD knew they couldn't ride Summit Ridge forever, so Zen+/Pinnacle Ridge was a cheap replacement for a product update. Cash flow may well have negatively affected all three of the Zen update teams. Also remember that AMD was stalled out by Globalfoundries and their failure to make 7nm work. AMD had (allegedly) already planned to move Rome to TSMC N7 (along with Vega20) well before GF threw in the towel, but that doesn't tell the entire story. In theory, had GF gotten their 7nm ducks in a row, we could have seen Matisse on GF 7nm much earlier than we saw Matisse on TSMC 7nm. In fact, at the time, that was one of my main assumptions as to why Matisse had taken so long and why we ever saw Pinnacle Ridge in the first place: in 2018, GF couldn't guarantee 7nm to AMD at any future point, so it was easier to sell a Pinnacle Ridge product on an improved GF 12nm process than it was to try and get Matisse to market ASAP. AMD also had a WSA to fulfill. That wasn't re-negotiated until GF proved they couldn't hold up their end of the bargain.

Kinda makes you wonder what process targets the Zen3 and 4 teams had before AMD knew that GF would go bust.

So, to summarize, I think Pinnacle Ridge happened because:

Cash flow made it difficult for the Zen2/3/4 teams to work at full pace until sales of Zen stabilized revenue
Zen2 was never going to be ready before Q4 2018 in any form (QS or otherwise) as result
GF couldn't guarantee a process for Zen2, but they could tweak 14nm into 12nm for an "easy" filler product

The confluence of factors made it inevitable that AMD would need Pinnacle Ridge. Note that Pinnacle Ridge was never used for EPYC. Now that AMD has a stable fab and has had decent-to-good cash flow for 2+ years now, there should be no further need for Pinnacle Ridge-like products.

Zen 1 was a completely new design, down to the lowest level libraries. It doesn’t seem unreasonable for that to take 5 years. Zen 3 is said to be a new architecture, but that mostly just means that they have made fundamental changes on how things work, but probably at the register transfer level. The low level libraries/macros/whatever are probably similar if not the same as Zen 2. It gets into semantics as far as what level of changes are required to be a “new architecture”. It isn’t going to be the same level as Zen 1, but it will still be significant differences.

 

[jamescox]

The space elevator was more of a joke compared to the rest but do remember that it was a "Space Race". Things were happening very rapidly back then. But things still take time.

I think a better argument to make is why did Zen+ have to exist? Because then we'd be on Zen 3 today with Zen 4 coming shortly. That seems to fit your cadence better. My guess is that AMD was so resource strapped that it couldn't follow up like it can now. They were also still working out the oddities of the new platform. Zen+ is what Zen should have been. Not to say Summit Ridge was bad though.

Now AMD has the luxury of deciding when to ship Zen 4 to an extent, as you said. I just hope that AMD remembers what happened last time they were on top. I think AMD's future is still bright with Lisa Su in charge.

AMD had to do a lot to spin off their fab as Global Foundries. Then, not to long after that, they had to switch from GF to TSMC since GF could no longer afford 7nm development. I assume that affected their schedules a bit. Making the IO die at GF and the CPU die at TSMC is a great strategy. The cpu die are tiny. While they are probably capacity constrained, having a cpu die that is only ~75 square mm allows them to make the best use of that capacity. I don’t really expect Zen 3 cpu die to be significantly larger than Zen 2. They both have the same amount of cores and cache, just arranged differently. That is a lot of die per wafer and the most common desktop parts use just one die. EPYC takes a lot of die, but the demand for server parts generally takes a while to ramp up. A lot of times, purchases plans are made well in advance. Even after Milan is available, they will probably mostly be still selling Rome for a while. The GPUs with their much larger die sizes seem like they would be eating up the largest amount of capacity. A 500 square mm gpu die is almost the size of 7 cpu die, so not far from a 64 core Epyc as far as fab capacity. The console parts are also quite large, but those mostly had to be produced quite a while before launch. The scheduling is probably a complicated mess, but I think they will have enough supply for a good launch.

 

[jamescox]

I'll believe that when I see it, but right now it looks like intel is going to struggle greatly to get any sort of meaningful volume out of 10nm even through '21. I'd really like them to come out with their MCM solution and keep up with AMD but it isn't looking so good for that any time soon.

Intels biggest threat in servers is falling behind in core count. Not because of AMD but because of ARM. With most people offloading FP heavy tasks to accelerators anyways, its often advantageous to have more cores than more FP width. This will become more true as time goes on as well, with all major players working on scaling up HSA designs. With ARM pushing out 192 core chips by 2022, even if sapphire rapids finally comes to fruition by then intel will still be behind arguably their biggest threat.

I do agree though that zen 3 should support more advanced instructions, and I think it will. Even though the perlmutter supercomputer listed milan as only being avx256, im fairly certain there will be some form of bfloat16/advanced vector support.

I don’t know if Intel really plans on making a 1D MCM solution? I was thinking that they will try to jump directly to 2.5 or 3D chip stacking. The problem (for Intel) is that TSMC appears to have a wide range of chip stacking technology in use and in the pipeline, some of it possibly superior to what Intel has been developing. Zen 4 is probably going to be stacked chips, which means more cores, more cache, and probably a lot of other things. Xeon already doesn’t compete very well with Rome. Milan will make Intel look even worse. I don’t know if Intel was planning on using chip stacking with 10 nm parts, so do we need to wait until Intel 7 nm is ready?

 

[Richie Rich]

You may just be Howard Hughes reincarnated If big is good, why not bigger? Practicality be dammed!. Then you end up with the Hercules which was useless.

All you say is 6x ALU, no 12x ALU, SVE 2048 bit, now it's 8192 bit wide AMX. Your posts are nothing more than entertainment point.

EDIT, and how could I forget SMT4? Still think we'll see that Thursday with Zen 3?

You sound like my 80- year old grandma, no offense.

I know your knowledge is usually very poor but I expected you know how to use google. I overestimated you again (last time you stated server market is bigger than smartphone market, when reality is smarphones are 7x bigger than servers). Here you are again, educate yourself:
AMX: "an 8-tile register file with each register being 16 rows x 64-byte (1 KiB) for a total register file of 8 KiB."

Advanced Matrix Extension (AMX) - x86 - WikiChip

Advanced Matrix Extension (AMX) is an x86 extension that introduces a matrix register file and new instructions for operating on matrices.

en.wikichip.org

• AMX: 8x registers with 8192-bit (16x512-bit matrix tile) .... total 64 kb
• AVX512: 32x registers with 512-bit vectors ......................... total 16 kb
• SVE in Fujitsu A64FX: 32x registers with 512-bit vect ........ total 16 kb
• ARM SVE2 maximum: 32x registers with 2048-bit vect....... total 64 kb
• AVX2 (AMD Zen2): 32x registers with 256-bit vect ............... total 8 kb

Zen3 without AVX512 is disaster. AVX512 was introduced in 2013 and if AMD cannot implement it after 7 years then it means AMX will be implemented in 2030? ARM Fujitsu CPU is destroying Nvidia's gigantic Volta GPUs in supercomputers thanks to matrix multiplication instructions. Intel, Neoverse, Apple and Nuvia will have MatMul in servers since next year.

Funny thing is that Jim Keller back in 2015 knew about MatMul SVE (officialy released in 2016, but developed 2014-2015). AMD could have MatMul SVE capable CPU in 2019 (K13). Now we can see how bad decision was to cancel K12. No wonder that Keller left. There is theoretical option Zen3 will have x86 version of SVE MatMul). But I doubt. IMHO Keller left because AMD canceled MatMul HPC uarch, he didn't care about ISA, whether its ARM or x86.

Just few days to confirmation Zen3 has SMT4!




Your insults are still not allowed here.


esquared
Anandtech Forum Director

 

[Thunder 57]

You sound like my 80- year old grandma, no offense.

I know your knowledge is usually very poor but I expected you know how to use google. I overestimated you again (last time you stated server market is bigger than smartphone market, when reality is smarphones are 7x bigger than servers). Here you are again, educate yourself:
AMX: "an 8-tile register file with each register being 16 rows x 64-byte (1 KiB) for a total register file of 8 KiB."

Advanced Matrix Extension (AMX) - x86 - WikiChip

Advanced Matrix Extension (AMX) is an x86 extension that introduces a matrix register file and new instructions for operating on matrices.

en.wikichip.org

• AMX: 8x registers with 8192-bit (16x512-bit matrix tile) .... total 64 kb
• AVX512: 32x registers with 512-bit vectors ......................... total 16 kb
• SVE in Fujitsu A64FX: 32x registers with 512-bit vect ........ total 16 kb
• ARM SVE2 maximum: 32x registers with 2048-bit vect....... total 64 kb
• AVX2 (AMD Zen2): 32x registers with 256-bit vect ............... total 8 kb

Zen3 without AVX512 is disaster. AVX512 was introduced in 2013 and if AMD cannot implement it after 7 years then it means AMX will be implemented in 2030? ARM Fujitsu CPU is destroying Nvidia's gigantic Volta GPUs in supercomputers thanks to matrix multiplication instructions. Intel, Neoverse, Apple and Nuvia will have MatMul in servers since next year.

Funny thing is that Jim Keller back in 2015 knew about MatMul SVE (officialy released in 2016, but developed 2014-2015). AMD could have MatMul SVE capable CPU in 2019 (K13). Now we can see how bad decision was to cancel K12. No wonder that Keller left. There is theoretical option Zen3 will have x86 version of SVE MatMul). But I doubt. IMHO Keller left because AMD canceled MatMul HPC uarch, he didn't care about ISA, whether its ARM or x86.

Just few days to confirmation Zen3 has SMT4!

Pretty sure I said "more lucrative" than smartphones. But hey, if we are going to start insulting each other than you are a joke. I think for whatever reason you like confrontation. You like to see just how far you can go. Just like that smiley-ass comment about SMT4. You know Zen 3 won't have it. What will you say when that becomes known? I mean if I can't use google than I guess you can't use youtube, because AMD spilled the beans on Zen 3 being SMT2 a long time ago.

 

[soresu]

AVX512 was introduced in 2013

Not a good point to make an argument with, considering how catastrophically fragmented HW support for AVX512 is in Intel's own products.

10G BASE-T ethernet was introduced in 2006 yet we still have few motherboards that support it in the consumer space, even compromise 2.5 and 5G standards have taken years to make any headway despite the continued troubles of WiFi requiring expensive mesh set ups to maintain a reliable, high bandwidth signal in any building not made out of purely plasterboard and wood partitions.

I probably got a bit off track with the ethernet comparison - but Intel's own foibles have limited AVX512 adoption, it really isn't something to stab at AMD about when they are doing so well without it.

 

[soresu]

Funny thing is that Jim Keller back in 2015 knew about MatMul SVE (officialy released in 2016, but developed 2014-2015).

If anyone knew about it in any detail prior to its official announcement outside of ARM Ltd it would be Fujitsu/Riken, not anyone working at AMD.

Even then I'm pretty sure that the Fujitsu/Riken partnership had a hand in the design of SVE in combination with the research that went into the ARGON research paper from years ago - hence them being the first off the bat in developing an SVE capable CPU.

I'm not sure where you got this strange idea of industrial omniscience about Keller, he is just a well paid employee of companies at the end of the day* - he is limited by what is announced by companies and published in academia, same as everybody else.

*since PA Semi let itself be acquired anyway, I think he was more of a partner in that arrangement.

 

[.vodka]

Not a good point to make an argument with considering how catastrophically fragmented HW support for AVX512 is in Intel's own products.

Yeah...

I mean, what a headache. I wouldn't touch that as a third party, not even with a laser pointer. Never know when Intel has a bad day and decides to add five or six more pieces to that puzzle and ruin your day.

Should AMD support it at some point? I suppose, but is it worth the effort? We'll soon know if they decided to dive right into this mess with Zen3...

Just three more days.

 

[eek2121]

A bit off topic, but it would be fun to speculate as to how Koduri could parlay this situation into becoming Intel's next CEO. Maybe in some other thread.



I've kind of wondered about that one myself.

The initial Zen team went as far back as 2012 when they hired Keller to build a team for a next-gen product. It took them five years to get ideas into working, commercially-available silicon. Five years. That's a long time, and it ought to tell you something about the state of AMD's CPU development team(s) in 2010-2012; that is, to say, they weren't doing very well at all.

Compare that to late 2018 when Rome was sampling and late 2019 when Milan was sampling, and you have a situation where AMD was able to move from Rome QS -> Milan QS in ~12 months. A massive improvement. Granted, Rome and Milan aren't so distant from one another in underlying design compared to Piledriver and Naples. Most of the groundwork for Milan has been laid out in the previous two generations of Zen. The question is, why the 2+ year delay between Naples and Rome?

I think it has more to do with when teams were put together and under what circumstances. AMD had major debt and not very much revenue in 2012, so Zen had to be developed on a comparatively shoestring budget. Eventually AMD convened teams for update products, and if I recall correctly, the teams were put together at about the same time. The teams were assigned to Zen2, Zen3, and Zen4, to keep the updates coming and keep AMD relevant at least as far out as 2021. Those dates have slipped a little into 2022.

In any case, with Zen, there was no guarantee of success or a future. There were also revenue problems until Ryzen and Naples CPUs could start selling. The Zen2 team may have taken as long as they did to produce working silicon due merely to resource starvation. It probably took over half a year or more of selling Zen to start seeing an appreciable uptick in usable cash-on-hand. AMD knew they couldn't ride Summit Ridge forever, so Zen+/Pinnacle Ridge was a cheap replacement for a product update. Cash flow may well have negatively affected all three of the Zen update teams. Also remember that AMD was stalled out by Globalfoundries and their failure to make 7nm work. AMD had (allegedly) already planned to move Rome to TSMC N7 (along with Vega20) well before GF threw in the towel, but that doesn't tell the entire story. In theory, had GF gotten their 7nm ducks in a row, we could have seen Matisse on GF 7nm much earlier than we saw Matisse on TSMC 7nm. In fact, at the time, that was one of my main assumptions as to why Matisse had taken so long and why we ever saw Pinnacle Ridge in the first place: in 2018, GF couldn't guarantee 7nm to AMD at any future point, so it was easier to sell a Pinnacle Ridge product on an improved GF 12nm process than it was to try and get Matisse to market ASAP. AMD also had a WSA to fulfill. That wasn't re-negotiated until GF proved they couldn't hold up their end of the bargain.

Kinda makes you wonder what process targets the Zen3 and 4 teams had before AMD knew that GF would go bust.

So, to summarize, I think Pinnacle Ridge happened because:

Cash flow made it difficult for the Zen2/3/4 teams to work at full pace until sales of Zen stabilized revenue
Zen2 was never going to be ready before Q4 2018 in any form (QS or otherwise) as result
GF couldn't guarantee a process for Zen2, but they could tweak 14nm into 12nm for an "easy" filler product

The confluence of factors made it inevitable that AMD would need Pinnacle Ridge. Note that Pinnacle Ridge was never used for EPYC. Now that AMD has a stable fab and has had decent-to-good cash flow for 2+ years now, there should be no further need for Pinnacle Ridge-like products.

Zen+ gave AMD the time needed to recoup their investment. What is notable is that Threadripper from Zen 1 had most, if not all of the latency improvements already. I suspect Zen+ was little more than a well binned Zen 1 product that incorporated the changes from Threadripper along with updated microcode.

Pretty impressive stuff if you ask me.

 

[moinmoin]

I'd love to know more about IceLake-SP. Still waiting.

It reportedly just got another delay. You'll need to wait one Q more according to Digitimes via Hardwaretimes. I reckon Intel needs your diligent push for it to keep up its cadence more than AMD.

 

[Markfw]

It reportedly just got another delay. You'll need to wait one Q more according to Digitimes via Hardwaretimes. I reckon Intel needs your diligent push for it to keep up its cadence more than AMD.

By the times it becomes available, Milan will be all over, and maybe even Genoa is it ?

 

[ModEl4]

A bit off topic, but it would be fun to speculate as to how Koduri could parlay this situation into becoming Intel's next CEO. Maybe in some other thread.

Please make the thread, btw does anyone knows how actually is the relationship between Raja and Lisa, I wouldn't like a repeat of the memory business 🤯

 

[turtile]

A bit off topic, but it would be fun to speculate as to how Koduri could parlay this situation into becoming Intel's next CEO. Maybe in some other thread.



I've kind of wondered about that one myself.

The initial Zen team went as far back as 2012 when they hired Keller to build a team for a next-gen product. It took them five years to get ideas into working, commercially-available silicon. Five years. That's a long time, and it ought to tell you something about the state of AMD's CPU development team(s) in 2010-2012; that is, to say, they weren't doing very well at all.

Compare that to late 2018 when Rome was sampling and late 2019 when Milan was sampling, and you have a situation where AMD was able to move from Rome QS -> Milan QS in ~12 months. A massive improvement. Granted, Rome and Milan aren't so distant from one another in underlying design compared to Piledriver and Naples. Most of the groundwork for Milan has been laid out in the previous two generations of Zen. The question is, why the 2+ year delay between Naples and Rome?

It normally takes 4-5 years to make a new architecture from the ground up. Also consider that they only had one team working on Zen 1 and ARM at the same time during those years. They actually had to scrap features for Zen 1 and move them to Zen 2 just to get the product out to market. Mike Clark said in an interview back around 2018 that they were already planning for the features in Zen 5. There was another interview with someone else that I think said that they will only make 5 iterations of an architecture and the move to a new one. Zen 5 should be the last of the Zen architecture if that is still the case.

The transition from Rome to Naples took so long were the fact that AMD had to move from GF, to a split between GF and TSMC to all TSMC (already mentioned). I assume moving to the new chiplet architecture, with its insane routing on the package, caused another delay.

 

[JoeRambo]

KL and KM part of that graph is irrelevant as those products are gone and did not have decent market penetration.

The only thing that matters is natural progression SKL-X -> CSL-X -> ICL and here Intel made unfortunate decision with AVX512_VNNI that is unfortunately not in Icelake.

That graph is a bit of memeish, cause good things are in F, CD, BW. The rest are either specialized instructions made to work on 512bits and most of them already exist in forms like BMI, BMI2 or some special algo accelerators like VAES/GFNI. Sure vectorizing stuff like integer
VNNI is the only important thing that is really unique and perf enchancing.

 

[turtile]

2018 for Zen 5:

 

[trexfromouterspace]

There was another interview with someone else that I think said that they will only make 5 iterations of an architecture and the move to a new one. Zen 5 should be the last of the Zen architecture if that is still the case.

Zen 2 was the last of the Zen architecture. Zen 3's from scratch and has no relation to Zen or Zen 2. It's only called "Zen 3" because of how successful the Ryzen branding has been.

 

[turtile]

Zen 2 was the last of the Zen architecture. Zen 3's from scratch and has no relation to Zen or Zen 2. It's only called "Zen 3" because of how successful the Ryzen branding has been.

Evidence? They only said the performance uplight is like a new architecture. It's still an evolution of Zen. If you watched the video I posted, they already laid out to Zen 5 before Zen 2 was released.

 

[Markfw]

2018 for Zen 5:

For those of us that are DEAF (literally), there is no CC in that video. Please summarize.

 

[Hitman928]

For those of us that are DEAF (literally), there is no CC in that video. Please summarize.

I think the point he was trying to highlight in the video is that in 2018 Mike Clark (chief Zen architect) said he had already begun working on Zen5 which shouldn't release until 2023 at the earliest. So again AMD started work on Zen 5 at least 5 years before it will come out.

 

[trexfromouterspace]

Evidence? They only said the performance uplight is like a new architecture. It's still an evolution of Zen. If you watched the video I posted, they already laid out to Zen 5 before Zen 2 was released.

Forrest Norrod

"When asked about what kind of performance gain Milan's CPU core microarchitecture, which is known as Zen 3, will deliver relative to the Zen 2 microarchitecture that Rome relies on in terms of instructions processed per CPU clock cycle (IPC), Norrod observed that -- unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs -- Zen 3 will be based on a completely new architecture."

Completely new architecture = not Zen. Doesn't get more obvious than that.

 

[etrin]

how long before the 50's drop?