Speculation: Ryzen 4000 series/Zen 3

[DrMrLordX]

Either you guys want leaks and get an excited NostaSeronx instead, or you have patience until October 8th instead.

Can we have leaks AND some patience? There's almost certainly going to be some questions left unanswered by the official launch presentation.

 

[Kenmitch]

Either you guys want leaks and get an excited NostaSeronx instead, or you have patience until October 8th instead.

NostaSeronx wild imagination/theories could explain why we haven't seen any leaks yet. AMD skipping the 4xxx naming?

5xxx series 5nm....Hmm?

Big Navi not so big....Hmm?

Hints?

You guys do realize the square root of 10 added to 8's rounded to the closest node is 5nm! /s

I'm not jumping on the train, but it would be somewhat a shocker if he turns out to be correct.

Of course it's best to wait for the 8th for clarification on Zen 3 at least.

 

[NostaSeronx]

There is also them hiring with 5nm in mind in Q1:
Austin => Join a global package reliability team that drives component and board-level reliability activities across AMD's 5nm/7nm IC and graphics-card products that employ advanced flipchip and chiplet package constructions.
Singapore => The Singapore-based Packaging Reliability Engineer would lead board-level reliability activities for 5nm/7nm AMD CPU/GPU/APU and graphic-card products

Hydrabad, India => Sep 2018 – Present. Front-end integration team: Synthesis over 7nm/5nm
Silicon Designer 2 => Physical Design CAD Engineer at AMD on the latest 5 nm & 7 nm FinFET based technologies
Senior Design Engineer => high performance Microprocessors,SERDES, DDRs, DAC's, ADC's, PLL's in tsmc7 and 5nm technologies.
=> May 2019 – Aug 2019. -Supported L3 Cache Physical Design team -Worked with the TSMC 7nm and 5nm
Layout Engineer => tsmc 5nm, 7nm
Silicon Designer 2 => TSMC (7nm, 6nm, 5nm)
Mask design technician => Jun 2019 – Present. Mixed-Signal layout design in 5nm/7nm FinFET technology
Physical Design Engineer => Five Successful Tapeout @7nm Technology. Starting @5nm Technology.
=> 2013-2018 => L2 Macro -5nm FinFET Test Chip Layout & SRAM Memory Compiler layout design in TSMC 5nm FinFET
Silicon designer 2 => Developing scripts in Python towards port migration of 7nm to 5nm using Python gdspy package.

Senior R&D Process Integration Engineer. TSMC. July 2017 – March 2018 which did N5 FEOL logic process integration became a Senior Product Development Engineer at AMD.
A&MS Layout Designer Engineer => N5 TSMC FINFET, HDSP, UHD2PRF and HDRF2P Testchip and compiler development from scratch for Hi-Silicon and AMD @Synopsys
Also, hired R&D Engineer II => Project/ comments: N5 for Hi Silicon and AMD

Zen3 at worst is 6nm EUV. With no improvement over Zen2.
Zen3 at best is 5nm EUV. With "tremendous" improvement over Zen2.

AMD showcased Vega 7nm before Apple A12 and showcased Rome 7nm w/ Vega 7nm after A12. It doesn't make sense for AMD to be behind in process node. Especially with a more simple and smaller die on a proven SP3/AM4 platform. Swap out 7nm, for easy 5nm gains with HMC SiGe PFET.

Navi2x is stuck on 7nm family;
7nm 3rd-generation DUV: PS5, XSX, XSS
7LPP RDNA2 IP for Samsung <-
5LPE RDNA2 IP for Samsung <- Both of these are identical so it is really Low-power 7LPP or High-performance 5LPE.

Zen3 so far on the APU side;
Rembrandt 40h-4Fh is 5nm, thus 50h-5Fh Cezanne is 5nm. Simply, because the model number is later. So, Zen3 IP is on 5nm.
We already have profiles "Experience in X86 PC Architecture Rembrandt APU of AMD processors" and an earlier pre-cleansed profile said Rembrandt is 5nm.

Van Gogh/Mero basically being the DDR4 version of 197.1 mm2 Lockhart-GDDR6 edition. Has Navi2x being 7nm as well.
Rembrandt having (LP)DDR4 [FP7] and (LP)DDR5 [FP7r2] being a true mainline processor is after the above. This means Navi3x is 5nm.

 

[.vodka]

Well Nosta, almost three weeks left for October 8. We'll see if your detective work pays off.

 

[NostaSeronx]

Well Nosta, almost three weeks left for October 8. We'll see if your detective work pays off.

If it doesn't pay off.

U87+U77+Custom = TSMC 5nm ... w/ Datacenter anytime after 2Q2021
N2+N1+Custom = TSMC 5nm ... w/ Datacenter anytime after 4Q2020

AMD has lost the server market to pipsqueaks with sovereign funds.

Doom and gloom 2H22 5nm. AMD not going to make 3nm, 2nm. TSMC has the nodes but AMD doesn't got the money.

2019... huh?

Be even more weird if it is October for 7nm(Gaming Zen3-Vermeer and Navi2x launch date) and January for 5nm(Compute Zen3-Milan and Arcturus launch date)

 

[deathBOB]

Apple Books TSMC's Entire 5nm Production Capability

Apple alone will soak up TSMC's 5nm capacity for the iPhone 12, iPad Air, and A14, leaving no room for anyone else.

www.extremetech.com

You must provide commentary with your OP/links.
No just dropping links or video.


esquared
Anandtech Forum Director

 

[NostaSeronx]

Apple Books TSMC's Entire 5nm Production Capability

Apple alone will soak up TSMC's 5nm capacity for the iPhone 12, iPad Air, and A14, leaving no room for anyone else.

www.extremetech.com

Apple isn't fully utilizing TSMC's 5nm.

They downgraded;
From ~45,000 wpq pre-Q4.
To ~20,000 wpq post-Q4.

While, AMD has upgraded;
From ~60,000 wpq pre-Q4. <== includes the Huawei shift to AMD for datacenter rather than using Hi1630. (Rome/Hi1620 = 7nm in 2018 ==> Milan/Hi1630 = 5nm in 2020)
To ~90,000 wpq post-Q4.

4Q19 for 5nm => 150K wafer starts per quarter (P1 done)
2Q20 for 5nm => 210K wafer starts per quarter
4Q20 for 5nm => 240K wafer starts per quarter (P2 done)
2Q21 for 5nm => 330K wafer starts per quarter
4Q21 for 5nm => 390K wafer starts per quarter (P3 done)

 

[Thunder 57]

@deathBOB I already mentioned that in this post.

Nosta just makes crap up. Where it comes from? I have no idea. It's best to ignore him.

Apple isn't fully utilizing TSMC's 5nm.

They downgraded;
From ~45,000 wpq pre-Q4.
To ~20,000 wpq post-Q4.

While, AMD has upgraded;
From ~60,000 wpq pre-Q4. <== includes the Huawei shift to AMD for datacenter rather than use Hi1630. (Rome/Hi1620 = 7nm in 2018 ==> Milan/Hi1630 = 5nm in 2020)
To ~90,000 wpq post-Q4.

4Q19 for 5nm => 150K wafer starts per quarter (P1 done)
2Q20 for 5nm => 210K wafer starts per quarter
4Q20 for 5nm => 240K wafer starts per quarter (P2 done)
2Q21 for 5nm => 330K wafer starts per quarter
4Q21 for 5nm => 390K wafer starts per quarter (P3 done)

Do you have a source for any of this?

 

[maddie]

@deathBOB I already mentioned that in this post.

Nosta just makes crap up. Where it comes from? I have no idea. It's best to ignore him.

Space-time traveler?

 

[NostaSeronx]

Do you have a source for any of this?

Digitimes => Apple orders 40,000-45,000 for Q1
Digitimes => Apple orders 20,000/5,000-6,000 for Q4

Chainnews and was validated => AMD orders 60,000 for Q2
udn and others also validated => AMD orders 90,000 for Q4+

On the TSMC N5 production numbers it is on anandtech and another place that OIP did.
September 2019 is when they started going from some wafers to 50,000 wafers. The same ramp that N7 did within three months for its ramp to 50,000 wafers.

Perception of TSMC's timetable of N5 is skewed. They think TSMC just started SRAM chips last year.

1Q2017 => "Now N5. ... Functional SRAM in our test vehicle has already been established."
2Q2017 => "Our 5-nanometer technology development is well on track, already with SRAM functional yield."
3Q2017 => "The world's first NXE:3400 EUV scanner has been released to production in our fab and has produced the best CD control, overlay and SRAM yield on our N5 technology. We have run over 1,000 backend yield trial lots of N5 with EUV and its yield is better than N7 at the same stage of our development."
4Q2017 => "Our N5 technology development is well on track for 1Q 2019 risk production. We already achieved good SRAM yield. Device development is also well on plan. Progress on both are similar to our N7 to the same development stage. N5 customer testchips are already running in our fab. We also made significant progress in improving EUV capability and the manufacturability. We have been consistently demonstrating high yield on N7+ and N5 development lots."
1Q2018 7nm+ break => "Since we maximize design rule compatibility between N7 and N7+, our customer can minimize the IP porting effort"
1Q2018 => "At N5, with more extensive use of EUV, we have obtained consistent double-digit yield on 256-megabit SRAM as well as our larger testchip."
2Q2018 => "Our 5-nanometer technology, N5 is progressing well. The 256 megabits SRAM yield is 1 quarter ahead of schedule, and the device performance is well on track."
3Q2018 => "Our N5 technology development is on schedule. We have completed the design solution development and are ready for customers' design start."
4Q2018/1Q2019 => Don't worry about it, it is pretty bland.
2Q2019 => "Our N5 technology has already entered risk production in first quarter. Customer takeout activity are underway"
Rest of it moves to N3 definition, etc.

 

[DrMrLordX]

Warhol is Zen3 on 5nm according to that one leak, and that doesn't come til maybe late H1 2021.

 

[NostaSeronx]

Warhol is Zen3 on 5nm according to that one leak, and that doesn't come til maybe late H1 2021.

Nope on that 5nm.







Dali's buddy is going to be a desktop CPU.
American Abstract Expressionist and Pop Art: Dali, Warhol, Pollock.

Two of them are Raven2, and there is no explanation why AMD popped out these:

https://www.amd.com/en/products/apu/amd-athlon-gold-3150g

https://www.amd.com/en/products/apu/amd-athlon-gold-pro-3150g

https://www.amd.com/en/products/apu/amd-athlon-gold-3150ge

https://www.amd.com/en/products/apu/amd-athlon-gold-pro-3150ge

https://www.amd.com/en/products/apu/amd-athlon-silver-pro-3125ge

(Athlon 200GE-300GE salvaged 4C/11CU die => Athlon 3000G 2C/3CU die)

Grey Hawk = 8C (Current spec) & 4C (Roadmap spec)
River Hawk = 4C? & 2C (Roadmap spec)
Given the above it makes more sense for Warhol to be River Hawk, imho.
(Athlon 3150-3125 salvaged 4C/11CU die => ??? 4C/3CU die)

If Vermeer had a refresh, why wouldn't it follow the pattern of Renoir's refresh?
Renoir -> Lucienne

 

[soresu]

If Vermeer had a refresh, why wouldn't it follow the pattern of Renoir's refresh?
Renoir -> Lucienne

I though Lucienne was embedded/ULP Renoir?

 

[uzzi38]

More likely situation IMO: Warhol is Zen 3 on AM5, allowing AMD to launch a DDR5 platform at the same time as Intel with Alder Lake (alongside other very nice platform features).

Also, Q3 2022 for Zen 4 is straight up not happening. That's out of cadence, and AMD ain't slipping any time soon.

 

[uzzi38]

I though Lucienne was embedded/ULP Renoir?

Nah, standard refresh. Will exist alongside Cezanne afaik as a more budget friendly chip.

 

[NostaSeronx]

That's out of cadence, and AMD ain't slipping any time soon.

imho, Zen3 being on 7nm is a slip up.

Bobcat/40-nm to Jaguar/28-nm => Evolutionary Re-architecture
Zen/14-nm to Zen2/7-nm => Evolutionary Re-architecture
New front-end
New execution core layout
Full width FPU, etc.

Most recent new revolutionary core from evolutionary/refined core was done in by GlobalFoundries poorly executing.
20nm Jaguar/ARM core -> 14nm Zen/ARM core

14nm = Zen / New architecture
12nm = Zen+ / Refinement
7nm = Zen2 / Evolutionary architecture
5nm = Zen3 / New architecture
5nm = Zen4 / Evolutionary & Refinement

Zen3 being developed from N5 spice v0.1 (New architecture that is of similar size as Zen2)
Zen4 then being developed from N5 spice v1.1 (This architecture shrinks Zen3 and increases and adds a couple somethings)

 

[Kedas]

AMD already confirmed 7nm for Zen3
and "tremendously" is taken out context:
All AMDs CPU products are tremendously powerful.

So you know that first Zen 1 Core was great and hugely cored, but Zen2 was as well. And Zen 3, that's at the heart of our next-generation products is also a tremendously powerful architecture and you know right on the trajectory that we needed to be

+10-15% be happy with it.

 

[NostaSeronx]

AMD already confirmed 7nm for Zen3

Then, they have slipped up. Competitors will be on N5, and they won't be.
If Zen3 is 7nm, then 5nm won't be seen till 2H22.

 

[uzzi38]

imho, Zen3 being on 7nm is a slip up.

Bobcat/40-nm to Jaguar/28-nm => Evolutionary Re-architecture
Zen/14-nm to Zen2/7-nm => Evolutionary Re-architecture
New front-end
New execution core layout
Full width FPU, etc.

Most recent new revolutionary core from evolutionary/refined core was done in by GlobalFoundries poorly executing.
20nm Jaguar/ARM core -> 14nm Zen/ARM core

14nm = Zen / New architecture
12nm = Zen+ / Refinement
7nm = Zen2 / Evolutionary architecture
5nm = Zen3 / New architecture
5nm = Zen4 / Evolutionary & Refinement

Zen3 being developed from N5 spice v0.1 (New architecture that is of similar size as Zen2)
Zen4 then being developed from N5 spice v1.1 (This architecture shrinks Zen3 and increases and adds a couple somethings)

Nope.

Zen 3 existing in it's current form in general is complete change of roadmaps. Zen 2 and Zen 3 both are entirely different to how they were both planned.

The change of plans was a good one though IMO.

 

[uzzi38]

Then, they have slipped up. Competitors will be on N5, and they won't be.
If Zen3 is 7nm, then 5nm won't be seen till 2H22.

Also no. Still 1H22.

Should be pretty obvious from 12-18 month cadence though. No such thing as slips on the Su train, that 12-18 month cadence is god.

 

[Markfw]

Then, they have slipped up. Competitors will be on N5, and they won't be.
If Zen3 is 7nm, then 5nm won't be seen till 2H22.

What competitors ? Intel won't be on 5 nm next year, they have not got 10nm or 7nm working on anything but a quad core ! You think they will be on 5 nm by then ??

 

[NostaSeronx]

What competitors ? Intel won't be on 5 nm next year, they have not got 10nm or 7nm working on anything but a quad core ! You think they will be on 5 nm by then ??

The ARM competitors will be on 5nm.
Apple's desktop SoC and GPU.
There is a datacenter 5nm ARM cpu with at most 160-cores. I am unsure if it includes SVE.

Zen 3 existing in it's current form in general is complete change of roadmaps.

Zen3 on 5nm is also very viable as design complete. Especially on its timetable of general availability in 2021.

N7+ <-> N5 isn't a huge gap.

Kirin 990 5G (7nm+)
- September 6th 2019

Unisoc T7520 (6nm/7nm+)
- February 26, 2020

Apple A14 (5nm)
- September 15, 2020

Do you not remember when these occurred?

We would have seen Milan or MI100 demos last year at least, if they were going to do N7-refined or N7+.

Being on 7nm in 2020 is bad execution and a slip up.

This whole October deal smells like E3 2016; Summit and Polaris reveals. GPUs got out on time, but the CPUs got pushed to the next year.

Failure to do a two year cadence for new nodes is a definite slip up. Especially, if the fab is running ahead of schedule.
2016 14nm
2018 7nm
2020 5nm
2022 3nm

https://forums.anandtech.com/attachments/earlynto-jpg.30132/

Zen3 on 7nm engagement in 2018 (Classic Development) => Thursday, January 9, 2020 tapeout
Zen3 on 5nm engagement in 2018 (Modern Development) => Sunday, August 4, 2019 tapeout

Top 10 Highlights of the TSMC 2018 Technology Symposium - Semiwiki

Here are the Top 10 highlights from the recent TSMC 2018 Technology Symposium, held in Santa Clara CA. A couple of years ago, TSMC acknowledged the unique requirements of 4 different market segments, which has since guided their process development strategy -- Mobile, High-Performance Computing...

semiwiki.com

"IP developed for the v0.1 PDK is available for early adopters" - 05-04-2018

Viability of 5nm Zen3 is more likely than 7nm+ Zen3. Which means Zen3 = 5nm and 7nm+ in August 2019 meant after 7nm, not on 7nm.

Q2 2017 = 7nm risk
Q3 2018 = 7nm+ risk
Q1 2019 = 5nm risk
Q4 2018 is the only separation from 7nm+ risk and 5nm risk.

Relative to 7nm family: 5nm is cheaper per transistor.

 

[uzzi38]

The ARM competitors will be on 5nm.
Apple's desktop SoC and GPU.
There is a datacenter 5nm ARM cpu with at most 160-cores. I am unsure if it includes SVE.
Zen3 on 5nm is also very viable as design complete. Especially on its timetable.

N7+ N5 isn't a huge gap.

Kirin 990 5G (7nm+)
- September 6th 2019

Unisoc T7520 (6nm/7nm+)
- February 26, 2020

Apple A14 (5nm)
- September 15, 2020

Do you not remember when these occurred?

We would have seen Milan or MI100 demos last year at least, if they were going to do N7-refined or N7+.

Being on 7nm in 2020 on bleeding-edge is bad execution and a slip up.

Well you're not wrong about Zen 3 on 5nm being viable, just like I said before, not the Zen 3 as we know and care about.

Apple will have desktop 5nm products but outside that? Not to mention Apple don't compete vs AMD or Intel. Competition implies there's a chance of either products being the better choice. For the Apple ecosystem, there is no longer any choice.

Outside of Apple, AMD's only ARM competitor is Ampere I think? Oh and someone else. As for how competitive they'll be only time will tell. And by time I mean 2H21, provided we don't get any leaks earlier.

Which, to be fair, we totally will.

 

[jamescox]

Well you're not wrong about Zen 3 on 5nm being viable, just like I said before, not the Zen 3 as we know and care about.

Apple will have desktop 5nm products but outside that? Not to mention Apple don't compete vs AMD or Intel. Competition implies there's a chance of either products being the better choice. For the Apple ecosystem, there is no longer any choice.

Outside of Apple, AMD's only ARM competitor is Ampere I think? Oh and someone else. As for how competitive they'll be only time will tell. And by time I mean 2H21, provided we don't get any leaks earlier.

Which, to be fair, we totally will.

Given what AMD has said, I expect all of the parts launching in October to be 7 nm. The first parts on 5 nm are likely to be the mobile APUs sometime in 2021, not 2022. This makes sense, since the mobile APUs are obviously much more sensitive to power consumption. AMD will probably be on 5 nm for mobile parts while Intel is still at 10 nm process, so they will still be ahead of Intel. They will not be ahead of ARM process-wise, but that is a different discussion.

There seems to be a Zen 3+ type chip (Warhol) on AM5 with DDR5 for mid 2021. That will be good to get the socket out there with DDR5 and get all of the issues worked out before Zen 4. If it is still on 7 nm then it may not be that much of an upgrade from the initial AM4 Zen 3, so it may be low volume pipe cleaning. I don’t know if they ever planned to shrink Zen 3 to 5 nm, but if 5 nm was looking good enough, they could have decided to do the shrink for Warhol. That decision would have been made some time ago. If they did decide to do that, then it may actually be taping out soon, which could lead to rumors. The lead times are so long, I think a lot of rumors have actually been people mistaking future parts for things that are coming soon. If Zen 3 is actually launching with parts available in October, not just announced, then they would actually have needed to stockpile them for the last couple of months, I would think.

Zen 3 is a new architecture, so staying conservative with the process tech is probably the best path, especially for Epyc. They can’t afford to have issues with Epyc when trying to break into the server market. This is another reason for keeping the Zen “chiplet” on 7 nm.

 

[A///]

Some guy on the reddit was posting date theories on when Zen 3 will launch. The posts were deleted by an admin but they were the last week of October, days prior to a RDNA2 announcement. It could have been Nosta now that I think about it.