Ajay
Lifer
- Jan 8, 2001
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Wait a minute. In the 2016/2017 time range, AMD had two design teams and one implementation team. You are trying to tell me now, that in four years, they've expanded to 5 design teams. Nutz.
Where in that article does an AMD official state or a statement quote from AMD guarantee a 12 month cadence plan? Even the charts don't show such a claim.Ahem
New AMD Ryzen and EPYC Roadmaps, Zen 4 and 5nm Genoa by 2022, Zen 3 and Milan in 2020
AMD drops the hammerwww.tomshardware.com
Zen4 in 2022 is a miss, plain and simple. It's time to stop making excuses for AMD while bashing Intel for their roadmap mishaps. They set a goal, and they missed it.
My understanding is the teams were always present but they were secondary, not in lead architectural roles. Even when they were it was for canned products.
For example:
India -> Amur core/soc lead
Israel -> Nolan core/soc lead
Boston -> Excavator core/soc lead
Sunnyvale -> Zen core/soc lead
etc..
Basically, AMD is finally running the same as 2010-2014. Except, it is only for a single core lineage this time.
Free from GlobalFoundries means they can be node aggressive and design aggressive.
Apple A12 launches -> AMD starts sampling 7nm.
Apple A13 launches -> AMD starts sampling 7nmP.
Apple A14 launches -> etc.
I don't see AMD running slower than the Mobile market. If there is a node and it has more than 10,000 wspm. Then, AMD will be on that node like a ruthless monster attacking a pesky "teen" in a horror movie.
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EUV is the plan or the presumed plan. The rumored, unconfirmed Warhol may be a short run on 6nm scraps. There are supposedly some decent performance benefits, and if 6nm stays on AM4, then it'll give last choice AM4 buyer some wiggle room without spending money on a new AM5 build.
12 to 18 months, actually. Which is why I don't understand people thinking it was a strict yearly cadence. We have this from Papermaster.
If I had to guess when parts launch. I'd say a week or two after the announcement with reviews going up in that time frame, and come the 28th, I suspect it'll be a same day launch. Enough time for reviewers to do all the hardware in a 2-3 week period. I wouldn't be surprised if reviewers are getting hardware at the end of this morning or early October. The 28th is a Wednesday. Zen 3 launching a few days before or the weekend preceding it makes sense if GPUs will be available same day or next day. There will be a 2-3 week gap between the 8th and the 28th, in which time Zen 3 reviews by sites such as AnandTech may go up. This gives everyone ample time to review both CPUs and GPUs unlike the Zen 2 launch mess which someone had to remind me about. I had it in my head that only Zen 2 flagships were up for sale, not the whole lineup.
They still stick true to their word when it comes to launching before consoles. I just find the timing of a late October launch a little sketchy. Either they know Nvidia have low numbers, they won't compete at all, or they feel very confident. Or some other random theory that'll probably get stolen from this thread and published on Wccftech as a fact.
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DrMrLordX
Lifer
- Apr 27, 2000
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I give up. I just posted roadmaps showing Zen4 before 2022, but nobody wants to listen. I can't even find the roadmap showing Zen3 through 2022 (dunno where Hitman got it), but the one I can find contradicts that. Oh well!
The roadmap shows 4 releases (Zen1->Zen4) in 5 years (2017->2022). Period. I don't know how much more simple it can get than that.
coercitiv
Diamond Member
- Jan 24, 2014
- 6,187
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Looks like AMD does these slides inconsistently, depending on what they mean to convey: something happening faster or something lasting longer.
On one side we have Zen 3 launch until the end of the year showed on the end of the scale:
On the other side we have AM4 socket support until the beggining of the year showed on the end of the scale:
Therefore, any promise that AMD makes based on a graph and not specific & clear language should always be interpreted in the most favorable way towards AMD marketing.
Hence, marketing graphs are not roadmaps.
DrMrLordX
Lifer
- Apr 27, 2000
- 21,620
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All AMD has provided in the last three years have been marketing graphs and vague open-to-interpretation comments in interviews. Which I guess is better than mentioning the year and quarter that you will launch a product, only to miss your target. Intel . . . *cough*
Could they have changed their priorities a little to get the next generation Ryzen 5000 mobile chip out sooner? Intel doesn’t seem like they are going to have that competitive of part in the server market anytime soon but gaining market share in the server market takes a lot of time. Many companies have things planned far in advance, so they will not switch for quite a while. If AMD wants to grab a lot more market share in the short term, then they need to take mobile market share. It would be great if they can get both the chiplet based Zen 3 parts and the monolithic Zen 3 based APU out at almost the same time. I don’t know if they had the resources to do that in the past. Perhaps they have more resources available since the designs for console chips were completed. That may explain some of the rumors of Zen 3 being a Ryzen 5000 rather than a 4000 part (Skipping 4000 name for desktop parts).
I don't know. Original Zen looks like 2018 and not 2017 on some of those slides.
Possibly. It's something I threw out there a month or two ago on here. It's possible, but it comes down to how many console parts have been shipped. AMD only needs to supply a few parts. Sony, for example, has a robot aided automated assembly facility for all their consoles. I don't know who or what Microsoft uses. Given timelines, Sony alone wants 10M consoles by March 2021, up from 6M earlier in the year. No idea about Microsoft. I imagine shipments to both companies began a long time ago to meet that demand.
Would Zen 3 mobile and APUs launched sooner than later be good? Yes, especially with Intel rumored to bring out an 8/16 Tigerlake. I say rumored despite them making a PR statement they would, but PR is PR, and they haven't really been good at delivering for a few years now.
Possibly. It's something I threw out there a month or two ago on here. It's possible, but it comes down to how many console parts have been shipped. AMD only needs to supply a few parts. Sony, for example, has a robot aided automated assembly facility for all their consoles. I don't know who or what Microsoft uses. Given timelines, Sony alone wants 10M consoles by March 2021, up from 6M earlier in the year. No idea about Microsoft. I imagine shipments to both companies began a long time ago to meet that demand.
Would Zen 3 mobile and APUs launched sooner than later be good? Yes, especially with Intel rumored to bring out an 8/16 Tigerlake. I say rumored despite them making a PR statement they would, but PR is PR, and they haven't really been good at delivering for a few years now.
Cezanne using Vega rather than RDNA2 seems like the sort of thing AMD would do if they wanted to get a quick refresh of Renoir out there in less than 12 months*.
*Edit as in 12 months from Renoir launch which was July.
Per their roadmaps, official or leaked. They keep improving Vega, but they might have a RDNA2 for mobile ready and go against the leaks/what they said. Renoir launched in March and May. Renoir is the same codename for their mobile processors as their APUs.
Looks like AMD does these slides inconsistently, depending on what they mean to convey: something happening faster or something lasting longer.
On one side we have Zen 3 launch until the end of the year showed on the end of the scale:
On the other side we have AM4 socket support until the beggining of the year showed on the end of the scale:
Therefore, any promise that AMD makes based on a graph and not specific & clear language should always be interpreted in the most favorable way towards AMD marketing.
Hence, marketing graphs are not roadmaps.
We talked about it when the Zen3 compatibility controversy was raging. AMD quietly started to shift their language/context on their roadmaps. As you can see in the fine print of the socket roadmap, it says AM4 socket support until 2020. In the newer roadmaps presented in 2020 they started to use "through" 2020 (or 2021/2022) when discussing the slides. Yes it is a very subtle and confusing change and AMD should make the roadmaps more visually clear to avoid the confusion, but they give the proper context when talking about the roadmaps, it's just that context doesn't get conveyed in the world's largest game of telephone that is the internet.
For future products AMD is clearly making things a bit vague because if they say 4Q2020 availability and then it is available Jan 1 2021 people will freak out about it being delayed and AMD's sky is falling and they can't execute, etc. Just like with Zen3, as the products near completion, they start to give more firm dates for launch.
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Gideon
Golden Member
- Nov 27, 2007
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Considering the outrage about Frank Azor's tweet, I don't blame them ... I mean, people really expected there will be a full announcement in a day with no leaks based on a single tweet?!? (compare to the leaking sieve that was Ampere announcement)
If it's a such a random tweet on a private account, it was bound to be an announcement of an announcement. That's at least what I expected (though I did expected RDNA2 to come a bit sooner, at around the date that Zen 3 reveal is).
Yeah, that's all I expected as well. You don't put out a veiled meaning tweet about something happening the next day if it's a major product announcement. It was always going to be a teaser or at best a launch date with no other info. When real info is ready to be announced, it will come officially, not through an ambiguous tweet on a personal twitter account. People get way too emotionally invested in this stuff, lol.
To me it was clearly the announcement of the date presentation of the new GPU architecture and lineup, the most people could expect by that tweet could have been a teaser of the architecture/features and MAYBE some actual performance/watt improvement figures. Expecting more than that it was simply unrealistic.
Zepp
Member
- May 18, 2019
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is this the explanation of what happened to 18h and why Zen3 is being called 19h?
Not really...
Family 18h is the original Zen family.
K18.0 => Zen1
K18.1 => Zen2
K18.2 => Zen3
etc.
Indicating bigger vector-widths. Zen1 = 128-bit FMAs, Zen2 = 256-bit FMAs, Zen3 = 512-bit FMAs.
I believe the switch to 17h and 19h occurred before the launch of Zen and Zen2 and Hygon.
The shift to 17h brought improvements to Zen/Zen2. The shift to 19h brought improvements to Zen3/Zen4.
19h is based on another ARM core. Zen is derived from K12(ARMv8) and Zen3 is derived from an unnamed core(ARMv8.3+SVE). This is also where the SMT4 part technically comes from as it is derived from Vulcan(JK(K7-K8 then @ Apple) for K12/BK(BC-JG then @ Broadcom) for the unnamed core). Given that, the core of 19h should at least have a unified scheduler; inline with Intel's Core architectures and VIA's cores. However, the big split is the issue ports of FPU is more like VIA's core design rather than Broadcom Vulcan/Intel Core.
In general => 17h execution core != 19h execution core.
Retire should be different.
Mappers should be different.
Schedulers should be different.
Issue width might be the same, but execution units will be different.
etc.
If the above isn't the case, it isn't a real Zen3 core. Rather, just a Zen2+ core being fitted into a Zen3 launch. Basically, being Bulldozer to Piledriver, which aren't physically the same cores between Orochi-B0/Orochi-C0.
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Renoir launched in March. Not July.
EDIT: Cezanne will either launch with Zen 3, or it will launch in March. I suspect they will launch it sooner rather than later so it matches the Zen 3 desktop cadence.
Oh and they will be ready to beat tiger lake. We already know they have working full speed silicon based on benchmark leaks. This implies it is close to release.
Cezanne was seen in A0 in november 2019 even before Renoir :
so it has been worked in parallel of Renoir ?
Ajay
Lifer
- Jan 8, 2001
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AMD went through some massive 'down sizing' plus those who left for better opportunities. AMD has noted itself that the Zen team was very small for a mainline CPU project. I seriously doubt there is any significant work CPU work being done besides the three mainline teams - well, maybe four new since AMD is putting more focus on mobile (I haven't read anything on how mobile is being handled). There are other teams working on related technologies for HPC, interconnects, chip stacking, etc.; but these are pretty small teams (like Boxborough, MA).
It seems like a lot of the console chips would have been made already, so there is some possibility that they have some more fab capacity available. The design team that was working on the console parts should have been finished a long time ago, so perhaps they do have resources to get it finished sooner rather than later.
The mobile parts are almost the same cores; half the cache and maybe some power tweaks, maybe less aggressive prefetch. They just need a new layout to integrate them with the IO bits. They should already have most of the work done. They would have already ported the IO to 7 nm For Zen 2 based APUs.
http://www.dolphin-ic.com/products/standard-cell/tsmc_5ff_cell.html // Aug 31, 2019
Zen2 => Cx=57-nm / M1=57-nm and M2=40nm/44nm
Zen3;
7nm+/5nm 57poly => Cx=57-nm / M1=38-nm // Major difference is M0/M2/M3/Fin Pitch/Fin Length between 7nm/5nm.
5nm 51poly => Cx=51-nm / M1=34-nm
It appears to reflect Synopsys libs on 6nm. So, it should be official in regards to what AMD has access to.
www.dolphin-ic.com
www.synopsys.com
Only showing 6-track.
Pretty sus for AMD to choose October. Which is also the month date for Apple's launch.
Be the first time AMD missed sampling on the same node w/ Apple on the GPU side. Since, returning to TSMC.
Vega20 N7 = 2018 / A12 N7 (MTS-ES Crash McCrashy also sampled in 2018 btw)
Navi1x N7P = 2019 / A13 N7P
Navi2x ? = 2020 / A14 N5
- 6-track, Ultra High Density (51nm and 57nm poly pitch)
- 8-track, High Performance & High Density (51nm and 57nm poly pitch)
- All tracks are available with 6nm channel length
- 6-track, Ultra High Density (57nm poly pitch)
- 7.5-track, High Performance & High Density (57nm or 64nm poly pitch)
- 9-track, Very High Performance & High Density (57nm poly pitch)
- Channel Lengths include 8nm and 11nm
Zen2 => Cx=57-nm / M1=57-nm and M2=40nm/44nm
Zen3;
7nm+/5nm 57poly => Cx=57-nm / M1=38-nm // Major difference is M0/M2/M3/Fin Pitch/Fin Length between 7nm/5nm.
5nm 51poly => Cx=51-nm / M1=34-nm
It appears to reflect Synopsys libs on 6nm. So, it should be official in regards to what AMD has access to.
7nm Standard Cell Libraries optimized for Low Power, High Performance & High Density - Dolphin Technology
Dolphin Technology provides SoC designers with Standard Cell Libraries optimized for low power, high performance and high density across a broad range of process technologies.
www.dolphin-ic.com
Foundation IP Selector
Find the best Memory Compiler, Non-Volatile Memory (NVM), and Logic IP solutions for your SoC design needs, by simply selecting your desired foundry process node
Pretty sus for AMD to choose October. Which is also the month date for Apple's launch.
Be the first time AMD missed sampling on the same node w/ Apple on the GPU side. Since, returning to TSMC.
Vega20 N7 = 2018 / A12 N7 (MTS-ES Crash McCrashy also sampled in 2018 btw)
Navi1x N7P = 2019 / A13 N7P
Navi2x ? = 2020 / A14 N5
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Exactly. That's what I've been saying. There's a new damning report out there right now that Sony has cut production for the current agreed upon term ending in March 2021 by 4M units. 11M is now the projected rate. Which meant they had at some point increased their projected order from 10M to 17M. This is the first I'm hearing about it because they increased from 6M to 10M a few months ago.
The issue they're stating is yield issues. However, a deeper dive into the article says they're having trouble reaching the clock speeds on the GPU. This isn't surprising. I doubt Microsoft is having such issues as they took a more mainstream and conservative approach to clock speeds for the GPU vs. Sony's 2.2+ Ghz.
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