Speculation: Ryzen 4000 series/Zen 3

[lobz]

https://twitter.com/x/status/1296526977076207620

looks like amd can include more cores per ccx in a same 7nm node?

It's been quasi well-known for a while that they'll unify the 8 core CCX and the respective L3 in Zen 3.

 

[moinmoin]

https://twitter.com/x/status/1296526977076207620

looks like amd can include more cores per ccx in a same 7nm node?

Cezanne supposedly is Zen 3, and Zen 3 unifies the L3$ so possibly unifies two 4c CCXs into one 8c CCX.

It's been quasi well-known for a while that they'll unify the 8 core CCX and the respective L3 in Zen 3.

Only the unified L3$ is publicly known at this point.

 

[Tuna-Fish]

Only the unified L3$ is publicly known at this point.

The L3 is what makes the CCX. AMD Zen cpus communicate between cores through the L3 cache (just like Intel ones do). There are no other links between cores. If you unify the cache, you are effectively unifying everything.

 

[moinmoin]

The L3 is what makes the CCX. AMD Zen cpus communicate between cores through the L3 cache (just like Intel ones do). There are no other links between cores. If you unify the cache, you are effectively unifying everything.

Fair point, though we don't know the implementation details yet. With 4c CCX the L3 slices are all connected directly. With 8 L3 slices doing that is unfeasible so there's either some sub-partitioning going on or they use a different approach altogether.

 

[Tuna-Fish]

Fair point, though we don't know the implementation details yet. With 4c CCX the L3 slices are all connected directly. With 8 L3 slices doing that is unfeasible so there's either some sub-partitioning going on or they use a different approach altogether.

It's really not. They are doing the communication in the upper metal layers on top of the L3 SRAM, there is plenty of room. Having each core be fully connected to each L3 slice doesn't even cost any additional power (over what having longer links due to large cache) costs, assuming every core only has the same peak throughput available to it.

 

[moinmoin]

It's really not. They are doing the communication in the upper metal layers on top of the L3 SRAM, there is plenty of room. Having each core be fully connected to each L3 slice doesn't even cost any additional power (over what having longer links due to large cache) costs, assuming every core only has the same peak throughput available to it.

The change from 6 (4 cores) to 32 (8 cores) links to ensure every slice is connected to every slice seems to me a rather huge change to be sure that this is no problem and without any additional power cost. If that's really no problem without any compromises, to what amount of cores is that scalable?

 

[lobz]

Cezanne supposedly is Zen 3, and Zen 3 unifies the L3$ so possibly unifies two 4c CCXs into one 8c CCX.


Only the unified L3$ is publicly known at this point.

That's why I never said publicly.

 

[LightningZ71]

The change from 6 (4 cores) to 32 (8 cores) links to ensure every slice is connected to every slice seems to me a rather huge change to be sure that this is no problem and without any additional power cost. If that's really no problem without any compromises, to what amount of cores is that scalable?

With the number of links growing at N-1 links per node, it gets out of hand very quickly. A 12 node system has 38 more links, and a 16 node system has another 54 links, which puts you at 120 links or so. That's not something you are going to do with direct links. While it's 28 links per 8 node system, it's only seven links per node with a minimum of two adjacencies in a 2d plane, meaning that you need only worry about your corner nodes having some very crazy routing. With two layers above and below, it's not an overly difficult connection problem.

However, going beyond that gets hairy. It's one of the reasons that Intel decided on a mesh for their very high core count dies.

 

[itsmydamnation]

surprised no one linked this:

AMD Ryzen 2021-2022 roadmap partially leaks - VideoCardz.com

Back in May, @MebiuW revealed a new codename for AMD Ryzen processor series – Warhol. Today the same leaker revealed a new part of the same roadmap. AMD Ryzen in 2021: Warhol, Van Gogh and Cezanne? As we learned from MebiuW directly, the full roadmap has already partially been confirmed, but...

videocardz.com

so im guessing Warhol is a DDR5 part on new socket with same chiplet but different IO die.
Ra.* looks to be the first Zen4 parts with Rembrandt , i wonder if Ra* will be I/O die, GPI die (navi3) , chiplet die while Rembrandt being a monolithic die targeting Mobile.

would have preferred Zen4 to be a 2021 product, hopefully its early 22.
i also wonder if whatever comes after VanGo is 8 core Zen3 and if Rembrandt is > 8 , both of those should be 5nm which could allow for that.

 

[A///]

surprised no one linked this:

AMD Ryzen 2021-2022 roadmap partially leaks - VideoCardz.com

Back in May, @MebiuW revealed a new codename for AMD Ryzen processor series – Warhol. Today the same leaker revealed a new part of the same roadmap. AMD Ryzen in 2021: Warhol, Van Gogh and Cezanne? As we learned from MebiuW directly, the full roadmap has already partially been confirmed, but...

videocardz.com

so im guessing Warhol is a DDR5 part on new socket with same chiplet but different IO die.
Ra.* looks to be the first Zen4 parts with Rembrandt , i wonder if Ra* will be I/O die, GPI die (navi3) , chiplet die while Rembrandt being a monolithic die targeting Mobile.

would have preferred Zen4 to be a 2021 product, hopefully its early 22.
i also wonder if whatever comes after VanGo is 8 core Zen3 and if Rembrandt is > 8 , both of those should be 5nm which could allow for that. If Raphael is client, does that mean iGPUs are coming back under AM5?

Looks like that is from the same Warhol leak from June.

 

[HurleyBird]

It's pretty hard to make sense of the weird Cezanne/Van Gogh thing tbh, bringing up two APUs where each one uses an old IP versus just bringing up a single APU that uses the best of both. It's like a doubling of expenditure for a halving of results.

Say for example, if AMD were more sure about Zen 3 than RDNA 2, then I could understand one APU with Zen 3 + RDNA, and another with Zen 3 + Vega. That would still feel a bit overkill, but you could at least rationalise it as AMD going after Intel's jugular on mobile no matter the cost.

The only thing I can think of that makes a lick of sense here is if Van Gogh is a console part AMD is bringing to PC (Surface?), and that outside the CPU area Cezanne shares almost exactly the same floor-plan as Renoir, with little to no improvements to uncore/graphics/io (if the slides are accurate, lack of LPD5 might suggest this), and is being rushed to market as quickly as humanly possible to compete with Tiger Lake. Even then, that seems a bit dubious since the threat from Tiger Lake isn't so much the CPU portion (at least while it's constrained to quad core), but the huge GPU uplift. Of course, back when things were being decided things might have looked otherwise.

The one thing that wouldn't make any sense to me would be spending so much seemingly redundant effort on APU development without a similar philosophy for chiplets. Eg. parallel development of 5nm and 7nm Zen 3 chiplets makes much more sense than parallel development of Zen2/Navi2 and Zen3/Vega APUs, because if those 5nm parts can come out even half a year earlier than they would otherwise that's a huge market advantage. So, I assume if AMD is doing parallel APUs, they're also doing that.

 

[A///]

Who knows what's going on at AMD. Zen 3 better wow the entire market. No point in being so quiet if the product's performance isn't amazing.

 

[itsmydamnation]

It's pretty hard to make sense of the weird Cezanne/Van Gogh thing tbh, bringing up two APUs where each one uses an old IP versus just bringing up a single APU that uses the best of both. It's like a doubling of expenditure for a halving of results.

I think Zen2 vs Zen3 will be about Core count. They probably dont want to waste resources on creating a 4 core Zen3 CCX

Vega vs RDNA2 i have no idea.

 

[randomhero]

I think Zen2 vs Zen3 will be about Core count. They probably dont want to waste resources on creating a 4 core Zen3 CCX

Vega vs RDNA2 i have no idea.

It could be for cpu part.

It sure is weird.

 

[Gideon]

Well 2022 is kinda expected considering and's cadence is closer to 15 months, rather than 12. But yeah, it should be early 2022.

As for Van Gogh ,ths looks to me like a premium mobile APU only (LPDDR4 and 5 only is a good indicator). Probably for premium 5hin and lights. Perhaps it has less cores, more CUs and possibly even a wider memory bus (6 LPDDR channels vs 4 for instance)

 

[DrMrLordX]

surprised no one linked this:

Warhol looks like a cop-out. The market will want Raphael and AMD won't be delivering it in 2022. Slightly off-topic since that's Zen4 (presumably) but still. AMD just stepped off their roadmap claiming Zen4 by the end of 2021. I am definitely not on-board with tme recycling designs like that (Matisse, Matisse XT; Vermeer, Warhol).

 

[NostaSeronx]

We have just received bad news.

AMD aren't going to be able to make timelines. They won't be able to use chiplets to jump node to node. It is simply too expensive, AMD is broke and they aren't going to keep up leading edge anymore. With this Frontier and El Capitan is planned to be delayed to 2023/2025 respectively.

7nm for 2019, 2020, 2021, 2022(APU). It is obviously more expensive to have 5nm APUs before 5nm CPU chiplets. So, Durango/Rembrandt aren't 5nm.

AMD's venture in 5nm full-fledged EUV is a failure just like everyone else. Failed, unyielding, test chips have doomed AMD to a later fixed 5nm node for 2022 CPUs and 2023 APUs.



I just have recieved an awful notice AMD CEO Lisa Su has had an internal company affair before becoming CEO and will be booted out of AMD immediately. /s

 

[mikk]

APU and CPU timeline differs in this Roadmap, Cezanne and Van Gogh likely early 2021 followed by Rembrandt in early 2022 (or some time in H1) while Warhol and Raphael are likely scheduled for H2 2021/H2 2022. Warhol is a refresh generation of Vermeer by the looks of it. If this is legit Warhol is going against Alder Lake-S in the desktop.

 

[jpiniero]

It's pretty hard to make sense of the weird Cezanne/Van Gogh thing tbh, bringing up two APUs where each one uses an old IP versus just bringing up a single APU that uses the best of both. It's like a doubling of expenditure for a halving of results.

The CVML thing makes me think Van Gogh is actually an product aimed at embedded.

 

[mikk]

The low van Gogh TDP could mean it's limited to 4 CPU cores. In this case it could be difficult competing with Tigerlake 4C which has a much better IPC.

 

[uzzi38]

It's an iGP focused part, in which it demolishes Tiger Lake. It's not even aimed at the same market as TGL-U but rather TGL-Y, if that.

For the CPU portion and generally for -U Tiger Lake will be competing vs Cezanne.

 

[mikk]

It's an iGP focused part, in which it demolishes Tiger Lake.

Interesting observation, did you see a test? Could you share the link? How many units it will have?

 

[RTX2080]

I went to check that roadmap's source Mebiuw on both twitter & weibo, from his tone it seems this is a pretty old roadmap which is from unknown place. And Van goh is likely for machine learning & vision computing(highly customized platform), that said it's not going into PC or laptop or sth else.

The date above(2020, 2021, 2022)seems being added by Videocardz.

 

[uzzi38]

Interesting observation, did you see a test? Could you share the link? How many units it will have?

Minimum 8 CUs, which is 512 shaders.

Don't worry about tests for the time being, just note RDNA's improvement to graphics and bandwidth efficiency over Vega. A 5600XT performs on par with a Vega64 despite just over half the CUs and just over half the memory bandwidth.

 

[uzzi38]

I went to check that roadmap's source Mebiuw on both twitter & weibo, from his tone it seems this is a pretty old roadmap which is from unknown place. And Van goh is likely for machine learning & vision computing(highly customized platform), that said it's not going into PC or laptop or sth else.

I have two points to make to that.

1. AMD's roadmaps in the last 2 years have changed incredibly drastically. I doubt any claims that this is very old, and even if it were it's most certainly not accurate. You've seen one of the changes to the roadmap in this thread I'm sure - Zen 3 was originally going to have SMT4, and AMD have talked about other changes such as Zen 2 getting the TAGE branch predictor of Zen 3.

2. The people that I've talked to that spend time on Weibo have said not to trust him as he's highly pro-Intel and has gone so far as to make up stuff regarding AMD to make Intel look better. Treat his roadmaps as something that need to be proved accurate first before we take then as anything remotely close to fact.