there you go
AMD Eng Sample: 100-000000114-07_22/15_N
AMD Eng Sample: 100-000000114-07_22/15_N
uzzi38
Platinum Member
- Oct 16, 2019
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Every single person in the rumour scene has been saying the same thing for a while. Getting any info from AMD is very difficult now. AMD are going to very great lengths to prevent any sorts of leaks.
Major Zen 3 leaks are not going to happen so easily. RDNA2 leaks probably won't happen until a week or two prior to launch (because there won't be any supporting drivers released to even OEMs).
Stop worrying about there not being leaks/samples. They exist and certain customers have them, you just won't hear about it for a while.
Anywho, I came to post this:
Major Zen 3 leaks are not going to happen so easily. RDNA2 leaks probably won't happen until a week or two prior to launch (because there won't be any supporting drivers released to even OEMs).
Stop worrying about there not being leaks/samples. They exist and certain customers have them, you just won't hear about it for a while.
Anywho, I came to post this:
DrMrLordX
Lifer
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Richie Rich
Senior member
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But K8 and K10 was still K7 based which was decade old microarchitecture. There was such a limiting things like ALU-AGU clusters. Intel's Core1 Yonah had modern decoupled ALUs and AGUs allowing to extract much higher IPC from code. Bulldozer had also this modern decoupled design (2xALU + 2xAGU), much wider OoO window and yet often much lower IPC than old K8/K10 (3x ALU-AGU).
I know you like BD, I guess you own one, but the truth is that 2xALU BD was awful design and huge step backward. Everybody expected 4xALU design in that time and if AMD did that, they would be 2 years ahead Intel's 4xALU Haswell (2013) and Apple's 4xALU A7 Cyclone (2013). This is the cause of 5 years of stagnation in x86 world what was presented as IPC wall, frequency wall and other Intel's BS. Best x86 core today cannot reach IPC/PPC of Apple A10 from 2015. That's a shame and evidence of design stagnation.
Apple's using core with 6xALU since 2017, Alpha EV8 was 8xALU in 2003.... how much evidence do you need that 2xALU design was outdated back in 2000. Same like 4xALU is outdated in 2020. From this point of view Zen3 has to be at least 6xALU design otherwise they will be in deep deep trouble.
DrMrLordX
Lifer
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Honestly dude, we've heard enough of that. Nobody really cares about that in the Zen3/Ryzen 4000 speculation thread anymore.
blckgrffn
Diamond Member
N7+ is better but neither of them are much better than N7 in my opinion, it wont change much if it's N7P or N7+, even N6. N5 would be exciting, though.
N7+ is better but neither of them are much better than N7 in my opinion, it wont change much if it's N7P or N7+, even N6. N5 would be exciting, though.
N7+ has few advantages over N7,N7P .
18% Higher logic density
1 fin transistor for use in non timing critical area.
Enhanced pattern fidelity and reduced process complexity (lower cycle time and higher wafer throughput due to EUV)
Tighter via resistance distribution due to better pattern uniformity
TSMC Technologies for Mobile and HPC - Semiwiki
During TSMC 2018 Technology Symposium, Dr. B.J. Woo, TSMC VP of Business Development presented market trends in the area of mobile applications and HPC computing as well as shared TSMC progress in making breakthrough efforts in the technology offerings to serve these two market segments. Both 5G...
semiwiki.com
I think the clock freq gain from N7 to N7+ is likely to be 200 Mhz for max freq and a larger gain of 300 Mhz for all core turbo. I would expect a 4.9 Ghz ST clock for the top bin Vermeer SKU. All core turbo could be 4.5 Ghz.
i'm looking forward to see if that holds true with zen 3 CCDs. technically 12LP was 10% denser yet zen+ SKUs have the same area than its zen 14LPP counterparts.
maybe it did shrink, but just CCX, cache and other parts except the I/O did, but it's not really noticeable.
maybe it did shrink, but just CCX, cache and other parts except the I/O did, but it's not really noticeable.
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Preventing leaks for a new chip typically means either:
- A: Preventing a demand-drop for the current generation from customers realizing they are buying soon outdated products.
- B: Preventing the competition from using that information to react to the new products early.
B (keep Intel in the dark) Is much more likely. AMD has successfully fooled Nvidia with Navi pricing. This time it may be Intel ...?
Zen 3 could be very big for AMD (and for us of course), if intel cant release rocket lake soon enough and zen 3 delivers what is expected then they have to play their cards very carefully. if all the techtubers recommend and label it as the ''best of the best'', single and multithread perforance, price-performance, power consumption, then intel lost. rocket lake wont change much after that even if it has better single thread perf, it will be a catch-up with worse power consumption (''14nm+++''), fewer cores, etc.
Their prime motivator 100% is demand drop. They're literally about to launch a ryzen 3000 refresh and potentially soon zen 2 apus. Ryzen 3000 sales are still incredibly strong for AMD right now, what better way to absolutely destroy their sales than to announce that zen 3 is only a few months away and it probably destroys zen 2 in performance.
They might also be playing a game with intel since rocket lake has also been pretty leak tight, but really IMO they're staying quiet because zen 2 is still selling very well and they don't want to hurt that.
DrMrLordX
Lifer
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Which is newer/better/more exciting? Were we hoping for one vs the other?
Definitely N7+ due to increased performance at isopower and increased density as well. AMD could relax their libraries a bit and still get higher transistor count plus a nice boost in clockspeed.
Zen + was basically Zen redux. Zen 3 is a new design so they'll use the full advantages of the node.
I haven't been following this at all, but what would be a reasonable expectation for performance? Will Intel have to give up the gaming crown? I'm stuck at nearly 2 yr old 9900K @ 5GHz and haven't used AMD since A64, will or should the new lineup be able to kick Intel down from the specific best case they have at the moment? If I can get 10 or 12 cores and indisputable better performance in the best Intel case (gaming) then I may actually consider Zen 3 whereas I earlier had resigned to not be able to get a worthwhile upgrade for 1-2 more years. Or is Zen 3 targeting something completely different?
blckgrffn
Diamond Member
This is exactly what Zen 3 is bringing to the table (fingers crossed). A likely 12-18 month superiority across the board, no matter how much power Intel is willing to pour into a 14nm+++++ Skylake derivative.
It's my opinion that Intel will come back swinging at some point, but it doesn't appear that will really be 2020/2021.
amrnuke
Golden Member
- Apr 24, 2019
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Maybe. That depends on their goal. Not maximizing transistor density may be one way of enabling higher clocks without being thermally limited.
We don't know enough details but I'd be incredibly surprised if they packed 100% of the transistors per mm2 onto the chiplets.
Nobody knows. Each generation naturally targets better performance but only independent reviews of the final product can show its strong and weak sides.
Zen 3 will have a unified 8c CCX, this will help thread jumping and utilizing the whole L3 for 8c models. However, the rest of latency problems will likely prevail. The IPC is gonna go up but how much particulary in games... dunno.
I'd say a 5GHz 9900K will be more than good for many years to come.
Aside from benchmarks it's unlikely you would see any difference while playing on or using your computer. Just go crazy on the GPU and enjoy.
Didn't exactly say that they would, although I now see that it could be seen as such.
How else would they fit in 12 ALUs so they can stop being lazy stupid x86 engineers?
amrnuke
Golden Member
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If 12 is good, surely 24 is better
Heck, why not toss SMT8 in there for good measure
If I can write it so easily, I don't see why it's such a hard thing for AMD and Intel to implement
Do to AMD's focus with gaming they should just integrate an Integer core into the RDNA's workgroup. They already use the same physical design techniques, SRAM, register files, etc. Then, allow the integer core to push fixed/float arithmetic instruction loads via translation logic units on to the local RDNA CUs. Thus, giving a logical core access to 64 ALUs!!!
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