Speculation: Ryzen 4000 series/Zen 3

[uzzi38]

Isn't the purported announcement day for the refresh some time soon?

There should be a few things happening on 6/16. I got a tip off there could be something this week as well. Maybe. Idk, the guy that told me has been very wrong on specifics beforehand, but usually gets official announcements correct.

Normally.

 

[jamescox]

I agree. It seems like a fairly substantial jump.

But here's my theory

• The IOD for Zen3 could possibly be fabbed by TSMC going forward. This could explain the jump in needed wafers because the IOD is not small.
  • Assuming worse density scaling than the CCDs because of the PHYs and IOs it will be bigger than the CCDs (80-100mm2 DT and 250-280mm2 EPYC)
  • This is bound to happen at some point. I am not sure GF can make the super dense micro bumps needed in the future for die stacking.
• The cores and cache grew in size for Zen3
  • Zen --> Zen2 core saw a growth of ~36% in transistor count including L3 cache. Just the core with the L2 it grew 17%
  • An increase in the CCD die size of 15% lets say means AMD would need 15% more wafers even keeping demand at same pace. And yield would drop even more.
• Additional wafer allocation for Q4 could be needed to cover additional products for Cezanne/Mobile APU. We know AMD has to be in time for OEM refresh otherwise they will miss the bus.

I don’t know if the chiplet die size will increase much at all over Zen 2. Zen 2 already has 32 MB cache per CCD (2 x 16 MB CCX) and the same number of cores. In Zen 3, it will all be unified into a single 8-core CCX, but it is still the same number of cores and L3 cache. It may be larger L2 size and the new architecture will take more transistors. Floating point hardware takes a lot of die area and there is a good chance Zen 3 has significantly increased FP power. I don’t know if they will go up to a full 4 AVX256 units. Some of the transistor count increase may be offset by denser process. Die size increase probably will not be due to L3 cache though, since it is actually the same amount per die. A larger cache size product may exists in some manner. That may be what the specialized super computer chips are. They could also possibly do something like Intel does (differing number of AVX512 units) and have a chip with more FP units. That gets complicated due to scheduler ports though. Initial Zen 1 was one die to do everything but AMD has a bit more money now, so they can afford to do more die variants to better cover the market.

I haven’t read this whole thread, so some stuff may have already been mentioned or debunked. I have ave been thinking that Zen 3, being a completely new architecture, will actually be very conservative in the initial release and use almost the same IO as Zen 2. Then Zen 4 will just be a shrink and/or slightly tweaked version of Zen 3, but with completely new IO die (pci-e 5, DDR5, etc). It may make sense for the Zen 4 EPYC IO die to be an interposer or just made of multiple chips. If they want to add L4 cache to the EPYC IO die for a more unified last level cache, then they would want to make them on a leading edge process for maximum density. It would also make sense to have them split into separate chips if they have a lot cache. Things get a bit crazy with an interposer or multi-chip IO die since there is a large number of possibilities.

I expected that the initial Zen 3 launch would be mostly EPYC and a small number of high end desktop parts. The Zen 2 XT parts are a bit confusing though. Are they going to release R9-4900 and R9-4950 in 6 months? I guess they may have just been getting high binning parts, so they decided to release some faster variants to look better against Intel and sell off some Zen 2 stock before Zen 3.

They could be working on a 5 nm APU based on Zen 3. If they have an 8 core single CCX Zen 3 APU, then would there be a reason to sell a single Zen 3 CCD + IO die for the low end desktop market? I guess I could see them making a 2 die APU also, with cpu + IO on one die and a small GPU die. That would allow for maximum flexibility, especially if they make a GPU die with an HBM stack.

 

[DrMrLordX]

Chiplet size may depend on process. N7P offers no density improvements over N7, but N7+ does . . .

 

[IntelUser2000]

@jamescox No chiplets for APUs, because they'll have to create another configuration.

The best we'll see is a Kaby-G style chip.

 

[LightningZ71]

I would like to think that there is still a possible place in the market for an APU that features a "Back side bus" for an additional memory bus to connect to an HBM stack. As a mental exercise, imagine that the next APU after Renoir was done on N5P. If it retained the 8 core configuration, moving to the single 8-core CCX and doubled the L2 cache to 16MB, there would still be enough die space for them to double the iGPU section to 16CUs and still keep the die size down to what it currently is or even smaller. Because the package itself won't change appreciably in size, there's not a huge push to reduce the die size to fit into a smaller one. However, if they came up with a new mobile package that has enough internal connections for an HBM stack, they could "easily" come up with a solution for mobile that gave performance in the x570/5500M range while only taking up a fraction of the board real-estate and power. There'd be no need for fancy chip and board technologies to manage the power split as it would all be on one chip. For additional power savings, in non-demanding situations, they could shut the HBM stack down completely and use just the main memory bus for screen buffering in 2D and in low performance 3D situations. As for on desktop, it would be seamless, as it would all be contained in the processor package. For lower end chips, there would be no need to include the HBM nor a reason to connect those pins on the die or activate that section of the die.

You REALLY want to stretch your mental legs? How about having an IF bus connection also available on the package? You could then use the same AM4/AM5 package to have an up to 8 core CPU that has an iGPU in low performance mode, a version that includes the HBM package for high performance iGPU applications, and another that includes a CCD that connects to the monolithic die to give it an additional 8 cores, and maybe even a full house package that has an HBM stack and a CCD. ITs all technically possible (though, pin out on the die would be brutal!).

 

[uzzi38]

Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct:

https://twitter.com/x/status/1270093432195895298

 

[RetroZombie]

And the tweet below that one:

https://twitter.com/x/status/1269968629963075585

 

[Ajay]

Chiplet size may depend on process. N7P offers no density improvements over N7, but N7+ does . . .

Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.

 

[soresu]

Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct:

https://twitter.com/x/status/1270093432195895298

Oof with that codename Lucienne - an illegitimate daughter of Renoir, says it all, don' it.

 

[soresu]

Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.

Depends, there is huge re use of the PHY going on between TB3, USB4 and Displayport 2.

This aught to count for something in IO size.

 

[NostaSeronx]

Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct

imho, it is more likely a refresh/respin of Renoir:
00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm

https://twitter.com/x/status/1214181557524738048

00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm

60F => K17.6
The 00/01/10/80 => Stepping
If 00 is Ax, 10 is Bx, then 80 is technically Hx of Renoir.

Guesses:
LPDDR5, I am unsure about DDR5, as the DCT/MCT architecture is slightly different in RN.
Reduced TDP, probably from an updated 7nm node, potentially EUV for extended long-term cost savings. (Renoir=pure consumer w/ Lucienne =more embedded focused, all features enabled(Embedded Qualcomm WLAN/BT, etc))

 

[IntelUser2000]

Depends, there is huge re use of the PHY going on between TB3, USB4 and Displayport 2.

This aught to count for something in IO size.

Thunderbolt 3 integration was a HUGE integration for Icelake. Yes it will impact die size.

But, weren't they talking about compute chiplets? In that case they won't be affected since they don't contain IO.

 

[LightningZ71]

I

imho, it is more likely a refresh/respin of Renoir:
00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm

https://twitter.com/x/status/1214181557524738048

00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm

60F => K17.6
The 00/01/10/80 => Stepping
If 00 is Ax, 10 is Bx, then 80 is technically Hx of Renoir.

Guesses:
LPDDR5, I am unsure about DDR5, as the DCT/MCT architecture is slightly different in RN.
Reduced TDP, probably from an updated 7nm node, potentially EUV for extended long-term cost savings. (Renoir=pure consumer w/ Lucienne =more embedded focused, all features enabled(Embedded Qualcomm WLAN/BT, etc))

I don't buy this as a simple "respin" of Renoir. 60F is base architecture of the core, but doesn't tell us a lot about the structure. With a rename like LN-A0, its a whole new die layout. With Renoir being a major redo of their APU line, this sounds like the same relationship that Raven2 was to Raven Ridge, about "half" the chip for low cost markets. So, a single CCX, up to 4CUs, perhaps a tweak for embedded use in some other parts.

I don't see the point in Renoir going for DDR5 right now. Even one year out, there will be precious few designs that include it in the mobile space. AMD's APU focus is Mobile first, at least, that's what it's been for the last few years, and I don't see it being applicable there more so than doing a 5nm update instead. I don't see DDR5 for Lucienne if it is just a cut down Renoir either, as that will absolutely have to be a low cost, life stable solution, and DDR5 would be FAR too cutting edge (in the mass market) for something like that.

I am happy to be proven wrong, but those are my feelings based on what we know.

 

[soresu]

Thunderbolt 3 integration was a HUGE integration for Icelake. Yes it will impact die size.

I meant in the context of reusing the PHY which is reused over at least 3 separate IO standards now since Intel opened up TB3.

That should at least defray the silicon cost of implementing DP 2.0 and USB 4 a bit if you already have TB3 support baked in.

 

[soresu]

I don't buy this as a simple "respin" of Renoir. 60F is base architecture of the core, but doesn't tell us a lot about the structure. With a rename like LN-A0, its a whole new die layout. With Renoir being a major redo of their APU line, this sounds like the same relationship that Raven2 was to Raven Ridge, about "half" the chip for low cost markets. So, a single CCX, up to 4CUs, perhaps a tweak for embedded use in some other parts.

Yeah, that would be a great base for some tiny SBC's.

8 cores is all well and good, but I could live with 4 to get a tiny board with passive cooling out of it - hail to the storm of AMD NUC's.

 

[NostaSeronx]

I don't buy this as a simple "respin" of Renoir. 60F is base architecture of the core, but doesn't tell us a lot about the structure. With a rename like LN-A0, its a whole new die layout. With Renoir being a major redo of their APU line, this sounds like the same relationship that Raven2 was to Raven Ridge, about "half" the chip for low cost markets. So, a single CCX, up to 4CUs, perhaps a tweak for embedded use in some other parts.

00810F11h => Raven Ridge
00810F80h => Picasso
00810F81h => Picasso
00820F00h => Raven Ridge 2
00820F01h => Raven Ridge 2

the 60 before the F means it is Renoir.

00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm

Means it is the same die just respun...
FX8100 (Bulldozer): 600F12 <== Zambezi
FX8300 (Piledriver): 600F20 <== Vishera (Same die, new FEOL)
A10 5800K (Piledriver): 610F01 <== Trinity (TN)
A10 6800K (Piledriver): 610F31 <== Richland (RL, Same die, new FEOL)
A10 7850K (Steamroller): 630F01 <== Kaveri, KV (GV, Godavari is probably 630F81)
A10 9700 (Excavator): 660F51 <== Bristol, BR (CZ, Carrizo is probably 660F01)
800F11 <== Summit, ZP
800F82 <== Pinnacle, PiR

Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.

I don't see the point in Renoir going for DDR5 right now. Even one year out, there will be precious few designs that include it in the mobile space. AMD's APU focus is Mobile first, at least, that's what it's been for the last few years, and I don't see it being applicable there more so than doing a 5nm update instead. I don't see DDR5 for Lucienne if it is just a cut down Renoir either, as that will absolutely have to be a low cost, life stable solution, and DDR5 would be FAR too cutting edge (in the mass market) for something like that.

Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.

Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).

JESD209-5 => February 2019
JESD209-5A => January 2020

• Additional power reduction functions including WCK power reduction
• Optimized Refresh
• Data/Byte selectable Write X
• Additional SI improvements
• ODT Rank to Rank turnaround improvement
• ODT function for CS pin
• Pin capacitance decrease

Changes added from 5 to 5A spec.

https://valid.x86.fr/nmltsi => Carrizo DDR3, 660F01
http://valid.x86.fr/m49wkt => Bristol DDR4, 660F51
As with these two, it has been done before, thus it can happen again between Renoir and Lucienne.

On another note I have seen mentions for a Zen3 APU for LPDDR5/DDR5/GDDR6 support(it has no support for DDR4 or LPDDR4(x)).
H-models => DDR5(SO-DIMM) or GDDR6(BGA)
U-models => DDR5(SO-DIMM) or LPDDR5(BGA)

 

[KOMACHI_ENSAKA]

Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct:

https://twitter.com/x/status/1270093432195895298

It's a Renoir Refresh (like Raven Ridge vs Picasso).
Different CPUs don't share the same CPUID.
We don't know yet if it's just a spin change or if it's a transition of N7 to N6.

 

[uzzi38]

It's a Renoir Refresh (like Raven Ridge vs Picasso).
Different CPUs don't share the same CPUID.
We don't know yet if it's just a spin change or if it's a transition of N7 to N6.

Yeah, someone else point out the same thing to me after. And I made the mistake of looking at Wikipedia that has the same CPUID listed for Dali and Picasso, so thought a smaller die was possible.

 

[DrMrLordX]

We don't know yet if it's just a spin change or if it's a transition of N7 to N6.

N6? Wow that would be interesting. I was thinking maybe N7P . . .

 

[Timorous]

Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.

There is no guarantee that it will.

Renoir has higher density than the Zen2 chiplets despite having less cache (typically very dense) and incorporating the IO (typically less dense).

 

[LightningZ71]

00810F11h => Raven Ridge
00810F80h => Picasso
00810F81h => Picasso
00820F00h => Raven Ridge 2
00820F01h => Raven Ridge 2

the 60 before the F means it is Renoir.

00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm

Means it is the same die just respun...
FX8100 (Bulldozer): 600F12 <== Zambezi
FX8300 (Piledriver): 600F20 <== Vishera (Same die, new FEOL)
A10 5800K (Piledriver): 610F01 <== Trinity (TN)
A10 6800K (Piledriver): 610F31 <== Richland (RL, Same die, new FEOL)
A10 7850K (Steamroller): 630F01 <== Kaveri, KV (GV, Godavari is probably 630F81)
A10 9700 (Excavator): 660F51 <== Bristol, BR (CZ, Carrizo is probably 660F01)
800F11 <== Summit, ZP
800F82 <== Pinnacle, PiR

Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.

Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).

JESD209-5 => February 2019
JESD209-5A => January 2020

• Additional power reduction functions including WCK power reduction
• Optimized Refresh
• Data/Byte selectable Write X
• Additional SI improvements
• ODT Rank to Rank turnaround improvement
• ODT function for CS pin
• Pin capacitance decrease

Changes added from 5 to 5A spec.

https://valid.x86.fr/nmltsi => Carrizo DDR3, 660F01
http://valid.x86.fr/m49wkt => Bristol DDR4, 660F51
As with these two, it has been done before, thus it can happen again between Renoir and Lucienne.

On another note I have seen mentions for a Zen3 APU for LPDDR5/DDR5/GDDR6 support(it has no support for DDR4 or LPDDR4(x)).
H-models => DDR5(SO-DIMM) or GDDR6(BGA)
U-models => DDR5(SO-DIMM) or LPDDR5(BGA)

Thank you for taking the time to explain this. I'm convinced. Taking everything you've pointed out into consideration, is it just possible that its just Renoir, but with the updated N7 process and no other significant changes? I can't imagine that an update to the LPDDR5 spec that was ratified in January would be on silicon in under a calendar year. Looking back at Raven Ridge -> Picasso, that wasn't a dramatic change to the die, but, aside from the move to GloFo 14 to 12 (which was more a tweak and less an actual shrink) and also more a refinement of various sections to improve power management and a few timings from what I know.

 

[Shivansps]

A reeplacement for Raven2 has to be coming somewhere in 2021, but it may be Picasso with a cut down IGP at 12nm, rather than "half Renoir" at 7nm. My guess is that it couldbe a 4C/4T/5CU Picasso at 12nm.

But Raven2 exists at 14nm because they needed to fulfill the contract, not sure if the same is true for 12nm, if not then it may be a half Renoir at 7nm.

 

[moinmoin]

Update regarding the previous N5P rumor: If AMD is ordering 5nm capacity for autumn this year at TSMC and working on 5nm based products, it is still not publicly mentioning it to investors. Last week AMD updated their corporate presentation, and Zen 3 (slide 13, 30), RDNA 2 (slide 16, 50) and CDNA (slide 18, 31) are all still listed as 7nm.

 

[french toast]

Update regarding the previous N5P rumor: If AMD is ordering 5nm capacity for autumn this year at TSMC and working on 5nm based products, it is still not publicly mentioning it to investors. Last week AMD updated their corporate presentation, and Zen 3 (slide 13, 30), RDNA 2 (slide 16, 50) and CDNA (slide 18, 31) are all still listed as 7nm.

Yea I saw that, however they mentioned 7nm for 'compute' amd overall Roadmaps, they did leave it out for one slide..one can dream..
In all seriousness I think we can put this N5P rumour to bed now.

 

[maddie]

Yea I saw that, however they mentioned 7nm for 'compute' amd overall Roadmaps, they did leave it out for one slide..one can dream..
In all seriousness I think we can put this N5P rumour to bed now.

Not me, dreaming is nice, most times at least.

All slides have node except client CPU. I have it now, they are the ones pushing the conspiracy to shake Intel's confidence. Sun Tzu stuff.