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Speculation: Ryzen 4000 series/Zen 3

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@uzzi38 "desktop Renoir is rumoured to launch alongside B550" => that would be nice with 3400G's supply chain issues (or what else has caused stock to dry up) and considering the new Ryzen 3 CPUs donot address the same (iGPU) need; leaving e.g. 2200G and 3200G to compete with Intel. Yet how confident are you about this rumour when the new consoles must hit the shelves in large numbers and taking Renoir laptop delays into account?

PS according to GN AMD's internal roadmap shows that APUs will have DDR5 in 2022. First time hearing about Zen 3+, maybe it's 7nm IP reused on N6? Is it possible for this (AM5) processor to work on AM4+ motherboards and Thursday's "big deal" reveal = B550 with AM4+ (or x670 with AM4+), cfr. AM3 processors with DDR2 and DDR3 memory controllers? Sorry about these wild guesses, blame it on corona.
 
Milan is shipping by late next Quarter for Cray it looks like. It will allow Cray enough time to assemble and ship it within Q4 for eventual deployment by year end.
Phase 1 of Perlmutter to be deployed in late 2020; GPU readiness efforts well underway
Click to expand...

NERSC Finalizes Contract for Next-Generation Supercomputer

NERSC has moved another step closer to making its next-generation GPU-accelerated supercomputer available to the science community this year. In mid-April, NERSC finalized its contract with Cray for the Perlmutter system, Phase 1 of which will be deployed in late 2020.
www.nersc.gov www.nersc.gov
Phase 1 will consist of 1500 Milan CPUs and 6000 Volta-Next
Each of Phase 1's GPU-accelerated nodes will have 4 of the next generation (Volta-Next) NVIDIA GPUs, along with 256GB of memory for a total of over 6000 GPUs. In addition, the Phase 1 nodes will each have a single AMD Milan CPU.
Click to expand...
Each of Phase 2's CPU nodes will have 2 AMD Milan CPUs with 512 GB of memory per node. The system will contain over 3000 CPU-only nodes.
Click to expand...
www.nersc.gov

Perlmutter System - NERSC: National Energy Research Scientific Computing Center

NERSC is the mission computing facility for the DOE Office of Science. Eleven thousand scientists working on hundreds of projects rely on NERSC to power their results.
www.nersc.gov www.nersc.gov
Video showing deployment of HPE Apollo Hawk in Stuttgart. The Perlmutter is a lot more sophisticated system.


You can kind of make a reasonable guess about Ryzen 4K from all of this.

Thanks to @kokhua for the news on Twitter.
https://twitter.com/x/status/1257490329923510272
 
uzzi38 said:
Just a little something I squeezed out of AdoredTV. Had a strong feeling it was the case with how late B550 is, but good to get confirmation.

This should also probably throw out any rumours that Zen 3 will not support AM4 or bresk backwards compatibility.

https://twitter.com/x/status/1257414380377059330

This is likely one of the things that will be discussed on Thursday.

EDIT: All I know of is that there is an embargo on Thursday to discuss something that could have easily been covered in the 3300X/3100 launch. I can't say I know specifics apart from one other thing - desktop Renoir is rumoured to launch alongside B550. Take that how you will.
Click to expand...
Funny, the guy from ADTV said Zen3 for 2020 is optimistic when AMD themselves said Zen3 in 2020 and that too in FAD no less just like you rightly said. Then next day, Perlmutter is planned to be deployed by late 2020.
And then in another tweet he asked Chia if the Perlmutter specs confirmed some of their leaks which we knew is from HPC Advisory council last year Oct 4 2019. They took the slides from that video removed the AMD watermark and posted it on their website as their "leak"
And another thing that is a common theme, that is so cringeworthy, they keep making up stuff like: yeah our sources ... yeah silicon is buggy, A0 no SMT, yeah power targets not met for Navi2X, B550 issues in HW, frequencies not decided.... An Engineer's day to day job is a leak.
By these standards, I have also "LEAKED" Zen3 last year Oct4 right here on AT Forums :laughing:
DisEnchantment said:
Video might get taken down


View attachment 11605


View attachment 11606




Zen 3 Milan highlights [AMD, Martin Hilgeman ]
- Unified L3 32+ MB per CCD
- Sampling already
- 7nm
- Same core count as Rome
- 2x SMT
- Planned for Q3 2020
- DDR4/SP3

What is Zen3's special sauce gonna be?
- Bigger cache most likely (32MB+)
- Improved IF
- ...
Click to expand...
 
DisEnchantment said:
Milan is shipping by late next Quarter for Cray it looks like. It will allow Cray enough time to assemble and ship it within Q4 for eventual deployment by year end.


NERSC Finalizes Contract for Next-Generation Supercomputer

NERSC has moved another step closer to making its next-generation GPU-accelerated supercomputer available to the science community this year. In mid-April, NERSC finalized its contract with Cray for the Perlmutter system, Phase 1 of which will be deployed in late 2020.
www.nersc.gov www.nersc.gov
Phase 1 will consist of 1500 Milan CPUs and 6000 Volta-Next


www.nersc.gov

Perlmutter System - NERSC: National Energy Research Scientific Computing Center

NERSC is the mission computing facility for the DOE Office of Science. Eleven thousand scientists working on hundreds of projects rely on NERSC to power their results.
www.nersc.gov www.nersc.gov
Video showing deployment of HPE Apollo Hawk in Stuttgart. The Perlmutter is a lot more sophisticated system.


You can kind of make a reasonable guess about Ryzen 4K from all of this.

Thanks to @kokhua for the news on Twitter.
https://twitter.com/x/status/1257490329923510272
Click to expand...
Looks like no AVX-512 for Zen 3.
Phase 1 of Perlmutter to be deployed in late 2020; GPU readiness efforts well underway
Click to expand...
Phase 2 is when the CPU nodes arrive though, and that's mid-2021.
 
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tamz_msc said:
Looks like no AVX-512 for Zen 3.

Phase 2 is when the CPU nodes arrive though, and that's mid-2021.
Click to expand...
There will be 1500 Milan CPUs and 6000 Volta-Next GPUs for Phase1 GPU nodes. For every 4x Volta-Next there is 1x EPYC.
Each of Phase 1's GPU-accelerated nodes will have 4 of the next generation (Volta-Next) NVIDIA GPUs, along with 256GB of memory for a total of over 6000 GPUs. In addition, the Phase 1 nodes will each have a single AMD Milan CPU.
Click to expand...
CPU only is for Phase 2. 3000 nodes, 2x EPYC per node.
 
uzzi38 said:
It's not just cloud infrastructure. The PC market in general benefits from the situation as more people staying at home means the need for a PC or laptop increases (god even just saying that feels wrong, but it is what it is).
Click to expand...
Maybe temporarily in March. By now, it should be declining due to all the layoffs and companies not wanting to spend cash to upgrade computers right now.
 
DrMrLordX said:
Exactly. That is what I mean. It would not surprise me at all if they have decided to neglect desktop APUs in this generation due to increased demand from OEMs. It is the same die. Demand for (and sales of) their desktop APUs have been tepid since they released Raven Ridge. The sales are probably good by Kaveri/Godavari standards, but today . . . ? No. And that is probably why we haven't seen a 4400G or . . . whatever they might call AM4 Renoir.
Click to expand...
Desktop APUs have always arrived significantly later than mobile APUs. 3000-series mobile APUs were launched at CES and started arriving in laptops in April-May or so. Desktop APUs hit the market in August or later. Given the CES launch of 4000-series mobile APUs and their arrival on the market in March, we're likely looking at a similar timeframe for 4000-series desktop APUs. Nothing at all unusual about that, and nothing indicating "neglect[ing] desktop APUs in this generation".
DrMrLordX said:
@Topweasel

Also, OEMs are not afraid to use laptop hardware in a desktop form factor if the price and performance are right. They don't need socket AM4 unless it offers some product advantage, like better cooling; lower prices; or better SKUs for their customer. Lots of desktop AiO solutions have mobile hardware in them. Well some of them do.

If AMD is able to sell all their Renoir dice in mobile form factor at attractive margins, they aren't going to want to repackage as many of them as 4000-series desktop APUs.
Click to expand...
It's true that OEMs aren't afraid of that, but it's more expensive (having to solder the APU to the board runs the risk of scrapping whole boards if the APU is defective) so they avoid it unless it is for some application where they find it makes more sense (such as SFF systems where they want the direct-die cooling). Using socket AM4 allows them to re-use motherboard designs, which saves money, and allows for further scaling of the same product line should they want to.

Tl;dr: there is zero indication that there won't be a Renoir AM4 desktop APU series.
DrMrLordX said:
@Shivansps

It is inaccurate to assume that continuing to use Vega would be a decision borne of "no demand for powerful iGPUs". AMD is going to continue to update Vega as a part of CDNA. The big question is whether or not updated CDNA will find it in any display-capable hardware. RDNA is allegeldy not compute-friendly, so I would not expect to find it in workstation cards and other professional dGPUs intended for display duty (which do exist, and have for some time). We already know Renoir has Vega and AMD has decided on Vega for mobile Renoir, so logically desktop Renoir - if/when it appears - will also be a Vega product. Whatever happens on the desktop will be an extension of whatever it is AMD decides is important for mobile - not for desktop. Desktop APUs are also-rans.
Click to expand...
I find it rather absurd to think CDNA - a datacenter compute centric spin-off of GCN - will find its way into APUs of all things. Even for a workstation APU the iGPU won't be big enough to deliver meaningful compute to the extent that a workstation needing GPU compute can skip the dGPU. And RDNA delivers perfectly acceptable compute performance, even if it isn't quite at GCN (or CDNA) levels per CU. And AMD has stated quite unequivocally that GCN is dead and that RDNA is their "GPU architecture for the next decade" - note the singular form of "architecture", indicating that no others will be carried forward and that CDNA is a compute accelerator architecture rather than a GPU architecture. Given that the main focus for APUs is integrated graphics for mobile and low-power applications (including Ryzen embedded and EPYC embedded) there is zero reason to think CDNA will be tapped for such a job - that's not what it's designed for. And GCN was warmed over for Renoir simply because the RDNA design wasn't ready for porting into the APU design when they needed it in the Renoir design cycle - 1 - 1 1/2 year (if not more) before launch, i.e. mid 2018 or earlier (a full year before the first RDNA dGPUs). Next gen APUs will 99% sure use RDNA, if for no other reasons than Intel finally becoming competitive on iGPU performance (but likely also to simplify future driver development).
 
Valantar said:
I find it rather absurd to think CDNA - a datacenter compute centric spin-off of GCN - will find its way into APUs of all things.
Click to expand...
I agree, we might see some 2.5D server chips down the line having CDNA chiplets (in fact this looks almost certain) but CDNA in a mobile or desktop APU is IMO also quite absurd. RDNA2 has enough compute perf and more importantly has all the required things for 3D rendering: TMUs, ROPs, Geometry/tessellation units possibly raytracing units (in APUs they migh skip these) ... all of these things will be removed for CDNA as they make no sense in datacenters. It would be quite strange if AMD decided to bolt them back on to a mainstream APU where 99% of the usecases won't benefit from the CDNA arch.
 
tamz_msc said:
Looks like no AVX-512 for Zen 3.
Click to expand...

This is a small disappointment. I don't think anybody expected 512bit wide FP units (that would be quite the die-space waster considering they just doubled them up in Zen 2) but supporting a subset of AVX-512 instructions with 256bit units would still have been quite useful for some workloads. CLANG/GCC have already made 256bit wide AVX-512 the default as Intel throttles on 512bit wide instructions. It's still often useful and would have allowed more widespread use earlier for the devs.

I can't find the tweet I saw a while ago, but even with just 256 bit wide AVX-512 some devs have gotten 30%+ perf gains due to some nice new instructions missing in AVX2.

Of course it's totally fine for AMD decide to skip the additional decoder complexity that AVX-512 presents, it's far from a critical feature. Why I find it a bit of a dissapointment is just that:
1. Even VIA has added some AVX-512 support in it's latest Centaur processors (with also just 256 bit wide vector units and a fraction of development resources)
2. It looks like even Intel Atom cores will have it with Gracemont

So it's certainly doable. With AMD it looks we have to wait till 2022 (Zen 4) to get the first processors with any support (which means it will take years before this can be the default-path for most x86 processors in executables)

Hopefully AMD used the resources well to either improve AVX2 workloads significantly or added some variable extensions themselves.
 
Valantar said:
Desktop APUs have always arrived significantly later than mobile APUs.
Click to expand...

Kaveri/Godavari wasn't laptop-first. Everything after that? Yeah. But that should tell you the difference between the AMD that takes desktop APUs seriously and the AMD that doesn't.

Tl;dr: there is zero indication that there won't be a Renoir AM4 desktop APU series.
Click to expand...

. . . eventually.

I find it rather absurd to think CDNA - a datacenter compute centric spin-off of GCN - will find its way into APUs of all things.
Click to expand...

We will see. I don't think anyone knows for sure what the CDNA/RDNA split is going to be like until we see CDNA products. If RDNA represents a compute performance regression vs. Vega20 on a per-CU basis, then some folks are not going to be happy.
 
DrMrLordX said:
We will see. I don't think anyone knows for sure what the CDNA/RDNA split is going to be like until we see CDNA products. If RDNA represents a compute performance regression vs. Vega20 on a per-CU basis, then some folks are not going to be happy.
Click to expand...

I don't see any reason to keep any graphics related silicon on CDNA (e.g. think Frontier and so forth) Nvidia also doesn't do that. My bet is that CDNA is with HBM and strictly without any graphics bits. For everything that needs graphics there are RDNA2 derivatives.

The fact that CDNA is "professional/datacenter" doesn't mean there won't be Radeon PRO or W serires cards with RDNA. In fact there already are. Even datacenter (cloud-GPU) stuff will certainly be RDNA.

What are the usecases where the RDNA compute perf will be a critical shortcoming in desktop/mobile workloads? Any real HSA stuff has so little traction RDNA2 will be good enough for it for years (it isn't even 0.1% of the usage IMO)
 
Gideon said:
I don't think anybody expected 512bit wide FP units
Click to expand...
Yeah, the scaling benefits of N7+ are just not enough to justify that leap - Zen 4 on the other hand with N5P should have that at least, Genoa should be a beast for encoding once SVT xxx are more optimised for AVX 512 than they are already, not to mention likely offline path/ray tracers too.
 
DrMrLordX said:
If RDNA represents a compute performance regression vs. Vega20 on a per-CU basis, then some folks are not going to be happy
Click to expand...
RDNA1, and specifically Navi12/GFX1011 in particular has more feature sets than Vega20/GFX906 except half rate DPFP.
Outside of DPFP, Navi12 should outperform Vega20 in all other aspects by virtue of higher clocks/CU and for the new mixed precision operations Navi12 will definitely beat it because of multiple ops getting executed at once.
So I think it should be fine in that perspective.

GFX908/Arcturus is the only GFX9 series that has way more feature set than Navi for pure vector math. It has MFMA with bfloat16 types. Even NVIDIA don't have that yet.
Dunno if AMD will add MFMA to their RDNA lineup. Then, other things like network workload distribution, networked coherency, XGMI and the like may not be that interesting for the Desktop.
 
DrMrLordX said:
If RDNA represents a compute performance regression vs. Vega20 on a per-CU basis, then some folks are not going to be happy.
Click to expand...
I don't see why, RDNA2 will likely have an 80 CU maximum at least, and possibly higher clock speeds - at worst whatever losses will be offset by gains in clock and raw silicon.

Besides which, I seem to remember the whole spiel over the wave32 design of RDNA being about higher efficiency, less wasted utilisation in the waves/warps or whatever they are called, it seems unlikely that they would have said that if they expect a significant drop in compute.

I expect that there may be some tasks which are better in wave32 and some better in wave64, only time and a thorough review of RDNA2 and CDNA will reveal the outcome, albeit not with ML which obviously will benefit from the tensor units in CDNA.
 
DisEnchantment said:
RDNA1, and specifically Navi12/GFX1011 in particular has more feature sets than Vega20/GFX906 except half rate DPFP.
Click to expand...
Not unexpected in general - I don't think that AMD have done many cards that even do half rate FP64.

I'm pretty sure Vega10 didn't, or Fiji - was there even one other card from AMD since Hawaii that could manage it?
DisEnchantment said:
It has MFMA with bfloat16 types.
Click to expand...
Machine Learning FMA? Matrix FMA?
 
Shivansps said:
Yeah exactly it the exact same die developed for mobile but with a diferent package, they dont develop APUs for desktop.
Is not the same as for example, Matisse, it shares most of the development but is not the same server CPU packaged for AM4.

APUs had been always like this, and if im not mistaken, OEMs always got the new APUs first, it looks like everything still the same to me. Maybe they just understimated the Picasso demand in desktop.
Click to expand...

To reinforce the point you are making.

Threadripper is to EPYC as desktop APUs are to mobile APUs.
 
DrMrLordX said:
On a per-CU basis, it's doing better than VegaFE with its 64 CU, but the 5700XT has a clockspeed advantage.
Click to expand...
Precisely - at worst it's not doing much better per CU, but with an 80 CU model and perhaps even higher clock speeds it will be a step forward, and then RDNA3 will be better still.

Having said that if the reports of Hopper being chiplet based are true, I hope that RDNA3 is too.

Methinks further GPU conversation should be moved elsewhere.
 
DrMrLordX said:
Maybe. Ultimately, the question is: what kind of iGPU will they put on Cezanne? Though I guess that's more applicable to a Zen5000 thread.
Click to expand...
Probably Ryzen 5000HS/S/U, and likely RDNA2 - true, full fat RDNA2.

RDNA1 was at best a proof of concept filler to branch time between Vega and the full uArch benefiting from their console SoC design work.

I think proof of concept works best as a description, because it is not drastically superior to Vega while accompanying a very significant change in uArch to wave32 execution - this being the foundation on which RDNA2 is laid.

Perhaps RDNA1 even represents the early proof of concept shown to both MS and Sony, with later improvements going into both as well as divergent tech solutions developed for (and with) each console vendor.

The true RDNA2 on PC I believe represents the best of what they could get out of both projects, so as speculated it may well be superior to either solutions coming to consoles.
 
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