Eh, translations on Asian languages still pretty much sucks. So it's hard to understand what is really being said.
That is the problem, IMHO (Lost In Translation!).
That is the problem, IMHO (Lost In Translation!).
If they do the below we can definitely say AMD has the winning strategy.
Like Milan on 7nm and Vermeer/Cezanne on 5nm.
2H2020 => Milan EUV at Fab 15
1H2021 => Vermeer/Cezanne EUV at Fab 18
2H2021 => Genoa at Fab 18 on another phase
1H2022 => Next (Zen4) CPU/APU at N3 Fab Phase 1
2H2022 => Next (Zen5) HPC CPU at N3 Fab Phase 2
N2 which is supposed to be N3 with nanosheets is supposedly 2023. Which will get its own fab in Hsinchu.
EPYC/Compute always get the latest core on a mature node. While, consumers get smaller dies/costs with mature cores on newer processes.
Like Milan on 7nm and Vermeer/Cezanne on 5nm.
2H2020 => Milan EUV at Fab 15
1H2021 => Vermeer/Cezanne EUV at Fab 18
2H2021 => Genoa at Fab 18 on another phase
1H2022 => Next (Zen4) CPU/APU at N3 Fab Phase 1
2H2022 => Next (Zen5) HPC CPU at N3 Fab Phase 2
N2 which is supposed to be N3 with nanosheets is supposedly 2023. Which will get its own fab in Hsinchu.
EPYC/Compute always get the latest core on a mature node. While, consumers get smaller dies/costs with mature cores on newer processes.
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amrnuke
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I really hope Zen3 is on N7+. I think if Vermeer delayed to 1H21 that would be a miss though.
Re: overall cadence, Zen -> Zen+ and Zen+ -> Zen2 both were >12 months. Seems Zen2 -> Zen3 will be as well. I don't see them picking up the pace as processes shrink, since there will inevitably be issues that pop up than we can't predict. But one can hope!
uzzi38
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Vermeer and Milan will be same node.
Cezanne is N7+.
The only one that has a chance of not being N7+ even assuming my wacky as all hell reading into the situation is accurate is Rembrandt. And to be fair, an N5 APU being used as a pipecleaner product wouldn't shock me in the slightest.
Also, one thing I wanted to add is that I'm not saying Zen 4 APUs will be the first Zen 4 product and will launch Q1 2021. There is a very, very non-zero chance that Zen 3 IP is compatible and being prepared for both N5 and N7+, and not because of this APU, but because of something else. I'll leave that bit to your imaginations.
It would also be on the 5nm FinFET node.
MTS-RTO as 4000 series // N6
VMR-5NM as 5000 series // N5
Milan would be Zen3 on a mature node. Potentially equal or greater than 77mm2 per CCD. <== lower product per wafer
Vermeer would be Zen3 on a new node. Potentially equal or greater than 55mm2 per CCD. <== higher product per wafer
The same works with a 7nm+ APU and 5nm APU that are spec'd the same. The 5nm one can use less wafers, get more product out sooner.
Also, hopefully 52 CU -> 36 CU -> 8 CU with 5nm FinFETs will lead to >2 GH base gpu clock rate and ~3 GHz boost gpu clock rate.
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Veradun
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That's what I read there but still, only a translation, so I wouldn't bet anything on it getting all the nuances of the original language
Holy heck. AMD already gearing up for N5??? The only N5 part on their roadmap is Zen 4... this would put them way ahead of their roadmap, right?
I thought for sure AMD would wait out the iPhone launch to begin N5. Maybe Huawei cutting orders opened the door for them to be a little more aggressive?
EDIT: Here's this for everyone else who doesn't speak Chinese. I don't know if their translation is accurate either. I think they're implying AMD has a special N5 process this year, different from N5P next year, that Apple is also using.
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amrnuke
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If they can slap Zen4 on N5 mid 2021, that's going to be a major coup.
If as NostaSeronx says, they delay Zen3 til early 2021 and put it on N5, that's going to be a major coup.
I'll hold my breath a little... could be an exciting September expo circuit.
moinmoin
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Sorry, Chia's translation is better, yours is mixing up some of the things.
- Huawei's 5nm cut is without a date. Capacity gap was filled by Apple anyway.
- For Q4 Apple asked TSMC to add 10k wpm 5nm (where it competes with AMD and others)
- TSMC has developed an enhanced 5nm specifically for AMD, which has a capacity requirement of no less than 20k 12-inch wpm (I think that just means having TSMC do some customization comes with the requirement of taking at least 20k 12-inch wpm, so that's what AMD takes)
- Huawei also lowered 7nm orders, which were filled by "big customers like Nvidia and AMD".
- As a result both 7nm and 5nm are fully booked until the end of the year.
- TSMC didn't comment on the report.
DeepL is pretty decent if you need to work with machine translations.
The first 5nm part will probably be a server GPU in 2021 with Zen 4 following in 2022.
That one part just means the minimum AMD had to commit to was 20k.
My initial reaction was that I have my doubts, but then I remembered that its possible they go chiplet for the server GPU. Although looking it seems that's unlikely yet either, with an updated version of Vega being their next HPC GPU, but I think even that talk was fairly old so maybe it changed since then. (Also I learned that Arcturus apparently is not an architecture, like Navi/Vega/Polaris, but rather is just a specific chip?)
Which, how many wafers would those supercomputers use up? Just a hunch that the specialized process might have something to do with those. Where, even if they wouldn't take that many wafers, AMD could likely use the extra production for other markets. So basically use those deals to get a specialized process and then use the specialized process for other chips that might be based on a lot of similar. Which, didn't AMD also say that they were working on some supercomputer sorta like dev kit (where companies could get a small scale version of the AMD stuff to trial performance, and then if they liked it could scale up by buying out from there).
DisEnchantment
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That's an interesting thought. It reminds me of Vega20.
For now it is a single chip, at least in amdgpu, but like they have done in the past they could add more when it is closer to launch.
But, it would be not surprising if Arcturus turns out to be CDNA at some point in the near future. This chip has so many new things compared to Vega 20 with over 8 months of commit history in LLVM and amdgpu. Just a reminder, ROCm compiler is forked from LLVM.
For the single Frontier machine, assuming CDNA is over 20 TF/Card and using Vega 20 as reference, at 5nm with 0.1 defects/mm2, if 90% of the compute power comes from GPU that is like ~750 wafers plus another few hundreds for the CPUs. So it is going to be much lower than the total 12k wpm they requested.
uzzi38
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DrMrLordX
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uzzi38
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Thunder 57
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uzzi38
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...I've been on mobile all morning, I'd completely forgotten the forums do what they do with Reddit. I'll fix it up now
Given this slide, it seems very likely to me:
AMD has historically always put the GPU part on the advanced node first. Considering that 5nm should be in production for a while at TSMC, it will likely have pretty good yields. I think CDNA will be on it first rather than RDNA.
uzzi38
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Given this slide, it seems very likely to me:
AMD has historically always put the GPU part on the advanced node first. Considering that 5nm should be in production for a while at TSMC, it will likely have pretty good yields. I think CDNA will be on it first rather than RDNA.
They're to be released at the same time. Zen 4 is late 2021 to early 2022 (more likely the former), RDNA3 should be the same sort of time. Both are on 12-18 month release schedules, and are releasing no more than a quarter or maybe two from one another this year.
Richie Rich
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Zen3 needs 12K microcode space instead 4K for Zen2. That's interesting. There must be a lot of new things in that uarch. Maybe three times more means Zen3 has SMT6?
https://www.phoronix.com/scan.php?page=news_item&px=AMD-Larger-Microcode-Linux
https://www.phoronix.com/scan.php?page=news_item&px=AMD-Larger-Microcode-Linux
inf64
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Zen3 has SMT2 still but it's a wider core with a 15%+ IPC. It will be a rough ride for intel until 2022.Zen3 needs 12K microcode space instead 4K for Zen2. That's interesting. There must be a lot of new things in that uarch. Maybe three times more means Zen3 has SMT6?
https://www.phoronix.com/scan.php?page=news_item&px=AMD-Larger-Microcode-Linux
Richie Rich
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15% IPC uplift for Zen3 is way too small for brand new uarch.
Alder Lake in H1 2021 with 40%IPC jump (Golden Cove) can bring rough ride for AMD.
DrMrLordX
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So? Who cares? That isn't the point of this thread anyway. And good luck buying Alder Lake in H1 2021.
At this point I'm not sure I would ask you what is a proper IPC uplift for a new uarch anyway.
And, in all fairness, that isn't the point of this thread either. Yeah Intel may have a rough time. Actually it's probably guaranteed. It really has more to do with how quickly Zen4 hits the streets. AMD has more to prove, though, and delays won't look good for them, regardless of what anyone else is doing.
If its 15% higher IPC , but consumes less energy while also clocking higher then all of a sudden 15% high IPC looks amazing. See this is your problem you pick the numbers you think are important and then hyperfocus on them at the expense of the bigger picture.
by your logic both cannon and ice lake should be a problem for AMD right now , and yet.....................
uzzi38
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It's H2 2021, not H1. Probably quite late in the year too (oh hey look, Zen 4 timeline!)
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